Metal interconnection with low resistance in a semiconductor...

Details Metal interconnection with low resistance in a semiconductor... Metal interconnection with low resistance in a semiconductor...

2002-04-30

2003-12-30

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S597000, C438S618000, C438S622000, C438S586000

Reexamination Certificate

active

06670268

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to metal interconnections in semiconductor devices. More specifically, the present invention relates to metal interconnections for bit lines having low resistance, and a method of forming the same. The present invention encompasses techniques for reducing resistance of bit lines and for providing advanced morphology of metal interconnections associated with bit lines.
2. Description of the Related Art
Conventionally, increased integration density of semiconductor devices causes the number of fabricating steps to increase and design rules to become more restricted and complicated. Design rules in manufacturing semiconductor devices, e.g., semiconductor memories, are most relevant to a width of conductive lines for interconnecting between active regions, such as bit lines, word lines, and metal lines, or to operable pitches between the conductive interconnection lines. While narrower widths (or dimensions) of interconnection lines are helpful to enhance integration density of semiconductor memory devices, increased resistance thereon may affect propagation efficiencies of electrical carriers such as voltage or current. Such an increase of resistance through interconnection lines degrades operating speeds in semiconductor memory devices. This is especially problematic, as most semiconductor memory devices need to be operable in a higher frequency.
Procedures for forming typical interconnection lines, or bit lines, in a semiconductor memory device as shown in
FIG. 1
, are shown in
FIGS. 2A through 2F
and
FIGS. 3A through 3F
.
FIGS. 2A through 2F
illustrate procedures to complete bit lines in a view taken along sectional line X
1
-X
1
′ of FIG.
1
.
FIGS. 3A through 3F
also illustrate these procedures in a view taken along sectional line X
2
-X
2
′ of
FIG. 1
, which is orthogonal to X
1
-X
1
′, both of FIG.
1
.
Referring to
FIGS. 2A and 3A
, a contact hole
12
for a polysilicon plug is formed by a photolithography process after evaporating a first inter-layer insulation film
11
on a substrate
10
. After depositing a polysilicon film on the first inter-layer insulation film
11
and the contact hole
12
, a polysilicon plug
13
is patterned by a photolithography process. Next, a second interlayer insulation film
14
is deposited on the first inter-layer insulation film
11
and the polysilicon plug
13
. A photolithography process is conducted to expose the polysilicon plug
13
by removing a portion of the second interlayer insulation film
14
on the polysilicon plug
13
, so that a bit line contact hole (DC: direct contact)
15
is formed. The bit line contact hole
15
may also be seen in a top elevation view as reference numeral
100
in FIG.
1
.
Referring to
FIGS. 2B and 3B
, a barrier metal
16
and a metal film
17
are sequentially deposited on the second inter-layer insulation film
14
and the bit line contact hole
15
. The barrier metal
16
is made of Ti/TiN film evaporated by CVD (chemical vapor deposition). The metal film
17
is made of tungsten (W) evaporated by CVD.
Referring to
FIGS. 2C and 3C
, a CMP (chemical-mechanical polishing) is carried out to etch the barrier metal
16
and the metal film
17
flat. After the CMP process, the barrier metal
16
and the metal film
17
remain only in the bit line contact hole
15
, forming a bit line plug
18
. The CMP process removes other portions of the barrier metal
16
and the metal film
17
on the second inter-layer insulation film
14
.
Referring to
FIGS. 2D and 3D
, a bit line metal film
19
is formed on the bit line plug
18
and the second inter-layer insulation film
14
. The bit line metal film
19
is a tungsten film evaporated by CVD, so that the bit line plug
18
is defined to fill the contact hole
15
.
Referring to
FIGS. 2E and 3E
, a capping layer
20
is deposited on the bit line metal film
19
. The capping layer
20
, made of a nitride, is utilized as a hard mask for a bit line patterning process performed in a subsequent step.
Finally, referring to
FIGS. 2F and 3F
, a photolithography process is used to pattern a bit line
21
(corresponding to reference numeral
110
shown in
FIG. 1
) formed from the bit line metal film
19
and the capping layer
20
.
However, in the procedure of forming the bit line
21
according to the processing steps shown in
FIGS. 2A-2F
(or
3
A-
3
F), there is a problem in that an over-etching occurs, which results in the removal of a portion of the CVD tungsten metal film
17
used for the plug
18
as shown in FIG.
2
F. The over-etching after bit line patterning arises from the fact that a width of the bit line
110
of
FIG. 1
(or
21
of
FIGS. 2F and 3F
) is intentionally defined to be narrower than a diameter of the contact hole
100
of
FIG. 1
(or
15
of
FIGS. 2F and 3F
) because the bit line becomes more slender according to an increase in an integration density. The undesirable over-etch of the plug metal film
17
causes a single-bit fail that degrades reliability of a memory device and may cause subsequent processing difficulties.
To overcome these difficulties, a method has been suggested that uses a barrier metal formed on the plug metal film (i.e., the CVD tungsten film) as an etch stopper to protect the plug metal film against over-etching.
FIGS. 4A-4F
and
5
A-
5
F illustrate steps in a conventional procedure that uses the barrier metal for protecting the plug metal film against over-etching.
FIGS. 4A-4F
illustrate processing steps and are shown taken along the sectional line X
1
-X
1
′ of FIG.
1
.
FIGS. 5A-5F
illustrate the same processing steps and are shown taken along the sectional line X
2
-X
2
′ of FIG.
1
.
Referring to
FIGS. 4A and 5A
, a contact hole
32
for a polysilicon plug is formed by a photolithography process after evaporating a first inter-layer insulation film
31
on a substrate
30
. After depositing a polysilicon film on the first inter-layer insulation film
31
and the contact hole
32
, a polysilicon plug
33
is patterned by a photolithography process. Next, a second interlayer insulation film
34
is deposited on the first inter-layer insulation film
31
and the polysilicon plug
33
. A photolithography process is performed to expose the polysilicon plug
33
by removing a portion of the second interlayer insulation film
34
on the polysilicon plug
33
, so that a bit line contact hole (DC: direct contact)
35
is formed. The bit line contact hole
35
may also be seen in a top elevation view as reference numeral
100
in FIG.
1
.
Referring to
FIGS. 4B and 5B
, a barrier metal
36
and a metal film
37
are sequentially deposited on the second inter-layer insulation film
34
and the bit line contact hole
35
. The barrier metal
36
is made of Ti/TiN film evaporated by CVD (chemical vapor deposition). The metal film
37
is tungsten (W) evaporated by CVD.
Referring to
FIGS. 4C and 5C
, a CMP (chemical-mechanical polishing) process is carried out to etch the barrier metal
36
and the metal film
37
flat. After the CMP process, the barrier metal
36
and the metal film
37
remain only in the bit line contact hole
35
, forming a bit line plug
38
. The CMP process removes other parts of the barrier metal
36
and the metal film
37
on the second inter-layer insulation film
34
, so that the bit line plug
38
is defined to fill the contact hole
35
.
Referring to
FIGS. 4D and 5D
, an additional barrier metal
39
is formed on the bit line plug
38
and the second inter-layer insulation film
34
. The barrier metal
39
is a titanium nitride evaporated by CVD. The barrier metal
39
acts as an etch stopper in a subsequent processing step of patterning bit lines.
Referring to
FIGS. 4E and 5E
, a bit line metal film
40
and a bit line capping layer
41
are sequentially deposited on the barrier metal
39
. The capping layer
41
, made of a nitride, is utilized as a hard mask for a bit line patterning process performed in a subsequent step. The bit line metal film
40
i

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