Merged bipolar and CMOS circuit and method

Details Merged bipolar and CMOS circuit and method Merged bipolar and CMOS circuit and method

1999-03-25

2002-03-05

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S203000, C438S236000, C438S327000, C438S374000

Reexamination Certificate

active

06352887

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor integrated circuits, and more specifically to integrated circuits that merge bipolar and CMOS technologies.
BACKGROUND OF THE INVENTION
Modern integrated circuits are typically based on either complementary-symmetry metal-oxide-semiconductor (CMOS) transistors or bipolar transistors. CMOS offers the advantages of a relatively inexpensive process, low power dissipation, and transistors that can be tightly packed and scaled. These features make CMOS a popular choice for very large scale digital integrated circuits such as those used in memory and microprocessor applications. Bipolar, on the other hand, is a preferred choice for analog applications because of its ability to provide high speed, high drive current, and good noise margin. Additionally, bipolar transistor junctions provide smaller threshold voltage variations and are therefore often used as voltage references.
So-called “BiCMOS” fabrication processes seek to offer the benefits of both transistor topologies on a single integrated circuit. BiCMOS processes in the past that have attempted to optimize both types of transistors have suffered from high complexity and hence a much higher cost than a standard high-performance CMOS process. Recent trends in the semiconductor industry toward low-voltage circuits with high signal-to-noise ratios have brought a renewed focus to BiCMOS circuits.
Performance has traditionally been commensurate with process complexity in BiCMOS circuits. Additional mask levels and dopant implant steps provided better isolation, latch-up protection, and superior bipolar performance.
FIGS. 1
a
,
1
b
, and
1
c
are examples of three prior art BiCMOS configurations described in “BiCMOS Technology and Applications”, A. R. Alvarez, ed., Kluwer Academic Publ., 1989, pp. 65-68. These figures illustrate the typical performance/complexity tradeoff. The structure shown in
FIG. 1
a
is a so-called “n-well” CMOS process that incorporates a simple npn bipolar transistor. The channels of MOSFET transistors in a typical CMOS circuit are often formed in doped regions known in the art as “wells”. In
FIG. 1
a
, the p-channel MOSFET is formed in an n-well, whereas the n-channel MOSFET is formed in the p− epitaxial layer. “Twin-well” CMOS incorporates a p-well for the n-channel device to allow further optimization of the n-channel transistor's performance characteristics. Additional wells also simplify device isolation.
In order to lessen the parasitic collector resistance and collector-base capacitance, more complex processes add a buried subcollector (n+) layer and substitute n-type epitaxial layers for the p− epi of
FIG. 1
a
. The buried layers help prevent latch-up, thereby allowing the use of a p− substrate rather than the p+substrate in
FIG. 1
a
. The bipolar transistor of
FIG. 1
b
has superior performance characteristics over the structure of
FIG. 1
a
at the cost of the additional mask levels and implants for the buried layer and the deep n+ collector contact. The structure shown in
FIG. 1
c
is a high-performance twin-well BiCMOS circuit requiring even more complex processing.
A need exists in the industry for a process for building efficient high-gain bipolar transistors in a high-performance advanced CMOS process to produce increased analog circuit performance and flexibility at a cost comparable to that of the CMOS process alone.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the invention, there is disclosed a method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region of a bipolar transistor and a p− well of an n-channel MOS transistor; and forming in a single implantation step a collector contact well of a bipolar transistor and an n-well of a p-channel MOS transistor.
In accordance with another preferred embodiment of the invention, there is disclosed a bipolar transistor. The transistor includes a collector region of a first doping profile within a semiconductor substrate of lighter doping and a base region between the collector region and a surface of the semiconductor substrate. The base region adjoins the collector region and extends to the surface. An emitter region adjoins the base region and also extends to the surface. A collector contact well region adjoins the collector region and the base region, and extends to the substrate surface as well. The well region has a doping profile characterized by doping concentrations lighter than doping concentrations of the first doping profile.
An advantage of the inventive concepts is that a bipolar transistor can be fabricated using a twin-well CMOS process.


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A. R. Alvarez, ed., 3.1 Evolution of BiCMOS From a CMOS Perspective, Kluwer Acad. Publ. 1989, pp. 65-68.
J. A. Bruchez, et al., The Philosophy of a Simple Collector Diffusion Isolation Bipolar Process, Solid State Technology/Aug. 1987, pp. 93-97.
Robert T. Havemann, et al., Process Integration Issues for Submicron BiCMOS Technology, Solid State Technology/Jun. 1992, pp. 71-76.

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