Memory with recessed devices

Details Memory with recessed devices Memory with recessed devices

2006-07-18

2006-07-18

Wilson, Christian D. (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S365000

Reexamination Certificate

active

07078297

ABSTRACT:
A memory cell includes devices having associated isolation recesses of differing magnitudes. The effective channel width of a corresponding transistor is substantially equal to a channel top surface width plus twice a sidewall width formed by the isolation recesses. In an SRAM cell, a latch transistor has a larger effective channel width than an associated pass transistor by forming larger recesses, and therefore larger sidewalls in isolation layers surrounding the latch transistor and limiting such recesses for pass transistors. During manufacture of the memory cell, a mask is used to mask an area of the pass transistor while exposing an area of the latch transistor. Accordingly, recesses in an isolation layer around the latch transistor are formed without affecting a corresponding area around the pass transistor.

REFERENCES:
patent: 6258673 (2001-07-01), Houlihan et al.
patent: 6316302 (2001-11-01), Cheek et al.
patent: 6534805 (2003-03-01), Jin
patent: 6559029 (2003-05-01), Hur
patent: 2003/0102518 (2003-06-01), Fried et al.
Yang, Fu-Liang et al.; “Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65nm CMOS Scaling”; 2003 Symposium on VLSI Technology Digest of Technical Papers; 2003; pp 137-138.
Yang, Fu-Liang et al.; “A 65nm Node Strained SOI Technology with Slim Spacer”; 2003; 4 pgs; IEEE.

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