Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-06-19
2000-12-05
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714719, 714738, G06F 1100
Patent
active
061580376
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a memory testing apparatus for testing a memory constructed in the form of a semiconductor integrated circuit (IC) (hereinafter referred to as IC memory), and more particularly, to a memory testing apparatus provided with a failure analysis memory for storing position information of a defective or failure memory cell in a tested IC memory.
BACKGROUND ART
Storage capacity of an IC memory is increasing more and more, and accordingly an increased IC chip area and formation of patterns at high density are required. As a result, there is an increased possibility that a reduction of the yield of IC memories caused by a very minute defect occurs. In order to prevent the yield of IC memories from being reduced, there are manufactured IC memories in each of which, for example, a failure memory cell can be electrically replaced by a spare or alternative memory cell (also called a relief line or spare line). The IC memory of this kind is called a memory of redundancy structure in this technical field, and a decision as to whether or not the redundancy-structured memory can be relieved is rendered by referring to failure information (positions of occurrences of failure memory cells, the number of occurrences of failure memory cells, and the like) stored in a failure analysis memory.
FIG. 6 shows a block diagram of a general construction of an example of a conventional memory testing apparatus provided with a failure analysis memory. This memory testing apparatus comprises a pattern generator 11, a logical comparator 12 and a failure analysis memory 13. The pattern generator 11 generates, in response to a reference clock from a timing generator not shown, an address signal, a test pattern signal, a control signal and the like all of which are to be supplied to an IC memory under test (hereinafter also referred to simply as memory under test) MUT as well as generates an expected value signal to be supplied to the logical comparator 12. The test pattern signal is applied to the memory under test MUT, and is written in an address of the memory under test MUT specified by an address signal applied thereto simultaneously with the test pattern signal.
The test pattern signal written in the memory under test NUT is temporarily stored therein and thereafter is read out thereof. The read-out test pattern signal is inputted to the logical comparator 12. An expected value signal from the pattern generator 11 is supplied to the logical comparator 12 where the test pattern signal read out of the memory under test MUT is logically compared with the expected value signal to detect as to whether or not there is an anti-coincidence or mismatch between both signals.
If both signals do not coincide with each other, the logical comparator 12 outputs a failure signal (failure data) having, for example, logic "1" (logic H) to the failure analysis memory 13 to store it therein at an address thereof specified by an address signal supplied through an address bus line 14 from pattern generator 11. Usually, when both the signals coincide with each other, the logical comparator 12 generates a pass signal which is not stored in the failure analysis memory 13.
In such a way, the information on failure memory cells in the memory under test MUT generated during a series of tests is stored in the failure analysis memory 13. After the tests have been completed, a failure analysis for the memory under test MUT is carried out with reference to the failure information stored in the failure analysis memory 13.
For this end, the failure analysis memory 13 has the same operating rate or speed and storage capacity as those of the memory under test MUT, and the same address signal as that applied to the memory under test MUT is applied to the failure analyses memory 13 from the pattern generator 11 via the address bus line 14.
The failure analysis memory 13 is initialized prior to the start of a test. For example, when initialized, the failure analysis memory 13 has data of logic "0s": written in all of the
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patent: 5841785 (1998-11-01), Suzuki
Advantest Corporation
Cady Albert De
Lathrop David N.
Ton David
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