Memory systems including defective block management and...

Details Memory systems including defective block management and... Memory systems including defective block management and...

2004-10-20

2008-12-30

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S710000

Reexamination Certificate

active

07472331

ABSTRACT:
A memory system may include a plurality of non-volatile memory cells and a memory controller coupled to the plurality of non-volatile memory cells. The plurality of non-volatile memory cells may be arranged in blocks with each block including a plurality of pages of non-volatile memory cells. Moreover, the plurality of non-volatile memory cells may include a plurality of data blocks of non-volatile memory cells, a plurality of reserved blocks of non-volatile memory cells, and at least one management block of non-volatile memory cells. The memory controller may be configured to receive a data address for a page of non-volatile memory cells of a data block during a memory access operation, and to determine if the page of non-volatile memory cells corresponding to the data address is identified as being defective in the at least one management block. If the page of non-volatile memory cells corresponding to the data address is identified as being defective in the at least one management block, the memory controller may be further configured to direct the memory access operation to a page of a reserved block of non-volatile memory cells. Related methods are also discussed.

REFERENCES:
patent: 5963488 (1999-10-01), Inoue
patent: 6000006 (1999-12-01), Bruce et al.
patent: 6040999 (2000-03-01), Hotta et al.
patent: 6237110 (2001-05-01), Lin et al.
patent: 6601132 (2003-07-01), Nomura et al.
patent: 6678785 (2004-01-01), Lasser
patent: 7151694 (2006-12-01), Meihong et al.
patent: 2002/0048202 (2002-04-01), Higuchi
patent: 2004/0085849 (2004-05-01), Myoung et al.
patent: 2004/0196707 (2004-10-01), Yoon et al.
patent: 11-134257 (1999-05-01), None
patent: 2001-154860 (2001-06-01), None
patent: 2002-108720 (2002-04-01), None
patent: 2002-133892 (2002-05-01), None
patent: 2003-223360 (2003-08-01), None
patent: 2004-103162 (2004-04-01), None
patent: 1020040042478 (2004-05-01), None
patent: 1020040087245 (2004-10-01), None

Affiliated with

Also associated with

Rating

Memory systems including defective block management and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory systems including defective block management and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory systems including defective block management and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4049225