Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-06-11
2008-10-21
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S733000
Reexamination Certificate
active
07441167
ABSTRACT:
Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.
REFERENCES:
patent: 5075892 (1991-12-01), Choy
patent: 5388104 (1995-02-01), Shirotori et al.
patent: 5740179 (1998-04-01), Dorney et al.
patent: 5959911 (1999-09-01), Krause et al.
patent: 5995731 (1999-11-01), Crouch et al.
patent: 6058495 (2000-05-01), Lee et al.
patent: 6400623 (2002-06-01), Ohno
patent: 6754116 (2004-06-01), Janik et al.
patent: 6777785 (2004-08-01), Shyu
patent: 6853597 (2005-02-01), Jain
Choi Hee-Joo
Ha Kae-Won
Kim Youn-Cheul
Lee Joon-Hee
Choi Monica H.
Samsung Electronics Co,. Ltd.
Ton David
LandOfFree
Memory module with parallel testing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory module with parallel testing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory module with parallel testing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3998967