Memory interface control circuit and memory interface...

Details Memory interface control circuit and memory interface... Memory interface control circuit and memory interface...

2006-05-02

2006-05-02

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S194000, C365S195000

Reexamination Certificate

active

07038953

ABSTRACT:
According to one embodiment, one variable delay circuit adjusts a data strobe signal to be delayed, a control circuit generates an auxiliary signal, another variable delay circuit adjusts the auxiliary signal to be delayed, a mask generation circuit generates a mask signal based on the delayed data strobe signal and the delayed auxiliary signal, and an AND circuit applies the mask signal to the delayed data strobe signal, thereby generating a data strobe signal without a glitch. A write address signal generation circuit generates a control signal for controlling a flip-flop group based on the data strobe signal without the glitch, and the flip-flop group stores read data according to the control signal. A selector selects data from among pieces of data stored in the flip-flop group according to the read address signal.

REFERENCES:
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patent: 6529993 (2003-03-01), Rogers et al.
patent: 6680869 (2004-01-01), Sonoda et al.
patent: 6708245 (2004-03-01), Okuda
patent: 2002/0118575 (2002-08-01), Sonoda et al.
patent: 2003/0031081 (2003-02-01), Suzuki et al.
patent: 2001-189078 (2001-07-01), None
patent: 2003-050739 (2003-02-01), None
patent: 2003-059267 (2003-02-01), None
patent: 2003-173290 (2003-06-01), None

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