Memory implementation for handling integrated circuit...

Details Memory implementation for handling integrated circuit... Memory implementation for handling integrated circuit...

2006-06-13

2006-06-13

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S723000

Reexamination Certificate

active

07062695

ABSTRACT:
The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The access control circuit may be further configured to redirect the access to a spare cell of the plurality of addressable memory cells.

REFERENCES:
patent: 6181614 (2001-01-01), Aipperspach et al.
patent: 6643195 (2003-11-01), Eldredge et al.
patent: 6728910 (2004-04-01), Huang
patent: 6801471 (2004-10-01), Viehmann et al.

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