Memory devices having power supply routing for delay locked...

Details Memory devices having power supply routing for delay locked... Memory devices having power supply routing for delay locked...

2005-04-19

2005-04-19

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C327S156000, C365S194000

Reexamination Certificate

active

06882580

ABSTRACT:
A memory device includes first and second power supply pads configured to be connected to a power supply. The memory device further includes a data output circuit that receives power via the first power supply pad and outputs data responsive to an internal clock signal, and a delay-locked loop (DLL) circuit that receives power via the second power supply pad independently of the first power supply pad and that generates the internal clock signal responsive to an external clock signal.

REFERENCES:
patent: 6008680 (1999-12-01), Kyles et al.
patent: 6288585 (2001-09-01), Bando et al.
patent: 6727739 (2004-04-01), Stubbs et al.
patent: 323352 (1997-12-01), None
Decision of the Intellectual Property Office, Taiwanese Application No. 092102657, Mar. 17, 2004.

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