Memory devices having bit line precharge circuits with off...

Details Memory devices having bit line precharge circuits with off... Memory devices having bit line precharge circuits with off...

2007-01-30

2007-01-30

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S072000, C365S154000, C365S189080, C365S194000

Reexamination Certificate

active

10783481

ABSTRACT:
A memory device having an off-current (Ioff) robust precharge control circuit and a bit line precharge method are provided. The precharge control circuit may be embodied as a delay circuit unit which receives and delays a precharge enable signal for a predetermined delay time; a NAND gate which receives the precharge enable signal and the output of the delay circuit; and an inverter which inverts the output of the NAND gate. The precharge control circuit may enable the word lines before disabling the precharge signal.

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Notice to Submit a Response for Korean patent application No. 10-2003-0036748 mailed on Jul. 28, 2005.

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