Memory device using a reduced word line voltage during read oper

Details Memory device using a reduced word line voltage during read oper Memory device using a reduced word line voltage during read oper

1997-05-19

1998-08-18

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 36523006, 36518911, 365190, G11C 11418, G11C 11419

Patent

active

057966516

ABSTRACT:
A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A drive circuit generates a reduced word line voltage to activate the pass transistor during a READ operation. The reduced word line voltage has a magnitude less than the magnitude of the bias voltage used to activate the pull-down transistor.

REFERENCES:
patent: 5570312 (1996-10-01), Fu
patent: 5633832 (1997-05-01), Patel et al.

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