Memory device having reduced layout area

Details Memory device having reduced layout area Memory device having reduced layout area

2003-02-10

2004-11-09

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S203000, C365S063000

Reexamination Certificate

active

06816416

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor memory devices, and more particularly, to the arrangement of circuits within a memory device having local input/output lines and global input/output lines.
BACKGROUND OF THE INVENTION
How circuits are arranged in semiconductor memory devices can affect their efficiency and level of integration, or layout area. The individual size and layout of circuits within the memory device, such as within the memory core, can have a substantial affect on the overall size of the resulting memory chip when the circuits are replicated in great numbers.
FIG. 1
is a circuit diagram of a conventional memory device.
FIG. 2
is a block diagram illustrating the arrangement of the conventional memory device of FIG.
1
.
The conventional semiconductor memory device
100
includes a memory core
110
, local input/output lines LIO and LIOB, global input/output lines GIO and GIOB, a conjunction circuit
180
, and a local-global multiplexer
190
. The memory core
110
includes a memory cell
120
, bit line equalizers
130
, a PMOS sense amplifier
140
, a transmission gate circuit
150
, a NMOS sense amplifier
160
, and a NMOS sense amplifier driver
170
for driving the NMOS sense amplifier
160
. The conjunction circuit
180
includes a local equalizer
185
.
The bit line equalizer
130
is adjacent to the memory cell
120
, and the PMOS sense amplifier
140
is adjacent to the bit line equalizer
130
. The transmission gate circuit
150
is adjacent to the PMOS sense amplifier
140
. The local-global multiplexer
190
is adjacent to the transmission gate circuit
150
. The local-global multiplexer
190
is in a different semiconductor layer, that is separate, from the layer in which the transmission gate circuit
150
is formed. The local-global multiplexer
190
is under the memory core
110
. As shown in
FIG. 2
, the local-global multiplexer
190
is adjacent to the transmission gate circuit
150
. The NMOS sense amplifier
160
is adjacent to the transmission gate circuit
150
, and the NMOS sense amplifier driver
170
is adjacent to the NMOS sense amplifier
160
. The bit line equalizer
130
is adjacent to the NMOS sense amplifier driver
170
.
As shown in
FIGS. 1 and 2
, the local equalizer
185
is within the conjunction circuit
180
. Accordingly, the circuitry of the local equalizer
185
and the conjunction circuit
180
may compete, during layout, for the same limited area within a layer and, during operation, the power available for the circuits and associated signal intensities may be reduced.
SUMMARY OF THE INVENTION
Some embodiments of the present invention provide a memory device having a memory core, a local equalizer, and a local-global multiplexer. The memory core is connected to local input/output lines and global input/output lines. The local equalizer is configured to precharge the local input/output lines. The global multiplexer is configured to alternately connect and disconnect the local input/output lines with the global input/output lines. The local equalizer is in a same layer of the memory device as the local-global multiplexer. Accordingly, during layout, area set aside on the layer used for the local-global multiplexer may also be used for the layout of the local equalizer, which may reduce the overall layout area of the memory device.
According to other embodiments of the present invention, the memory device further includes a conjunction circuit and a polysilicon layer. The conjunction circuit is adjacent to the local equalizer, and is configured to control the memory core. The polysilicon layer extends between the conjunction circuit and the local equalizer to conduct a gate control signal therebetween. Accordingly, with the conjunction circuit adjacent to the local equalizer, a polysilicon layer may be used to conduct a gate control signal therebetween.
According to yet other embodiments of the present invention, a memory device includes a local equalizer, a local-global multiplexer, and a sense amplifier driver. The local equalizer is configured to precharge local input/output lines. The local-global multiplexer is configured to alternately connect and disconnect the local input/output lines with global input/output lines. The sense amplifier driver is configured to drive a sense amplifier, and is in a same layer of the memory device as the local equalizer and the local-global multiplexer. Accordingly, during layout, area set aside on the layer used for the local-global multiplexer may also be used for the layout of the sense amplifier driver and the local equalizer, which may reduce the overall layout area of the memory device.


REFERENCES:
patent: 6272062 (2001-08-01), Mueller et al.

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