Memory device employing dual clocking for generating...

Details Memory device employing dual clocking for generating... Memory device employing dual clocking for generating...

2007-12-18

2011-10-25

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S758000, C711S154000

Reexamination Certificate

active

08046665

ABSTRACT:
A memory device may include a memory core block, a data patch unit, a Cyclic Redundancy Check (CRC) generating unit, and/or a serializer. The data patch unit may be configured to patch parallel data read from the memory core block in response to a first read pulse. The CRC generating unit may be configured to generate the CRC code based on the parallel data in response to a second read pulse, the second read pulse delayed by a period of time from if the first read pulse is generated. The serializer may be configured to convert the parallel data to serial data in response to the first read pulse, and/or arrange the CRC code in a order for a number of bits of the serial data to generate a systematic code.

REFERENCES:
patent: 5056089 (1991-10-01), Furuta et al.
patent: 7088632 (2006-08-01), Pelley
patent: 7221613 (2007-05-01), Pelley et al.
patent: 7480282 (2009-01-01), Clune et al.
patent: 7656983 (2010-02-01), Klowden et al.
patent: 61-278100 (1986-12-01), None
patent: 1020030080587 (2003-10-01), None

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