Memory device and method for precharging a memory device

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S205000, C365S230020

Reexamination Certificate

active

07599237

ABSTRACT:
A memory device having a short precharge time is included. The memory device selects at least two pairs of bit lines and connects the selected two pairs of bit lines to the sense amplifier within a preparatory period during which the two pairs of bit lines and an input to the sense amplifier are precharged. In the preparatory period an input unit of the sense amplifier is precharged through by a plurality of precharge units through more than two bit lines, and thus the precharge time may be decreased. The memory device selects one pair of bit lines and connects the selected pair of bit lines to a sense amplifier within a read/write (data transmission) period.

REFERENCES:
patent: 6091620 (2000-07-01), Kablanian
patent: 6418067 (2002-07-01), Watanabe et al.
patent: 6836446 (2004-12-01), Hira et al.
patent: 2002-170388 (2002-06-01), None
patent: 1997-0076832 (1997-12-01), None
patent: 1020020002671 (2002-01-01), None
patent: 1020060063217 (2006-06-01), None

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