Memory device and fabrication method thereof

Details Memory device and fabrication method thereof Memory device and fabrication method thereof

2007-05-29

2007-05-29

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S954000, C257SE21179

Reexamination Certificate

active

11048852

ABSTRACT:
A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

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patent: 6667511 (2003-12-01), Fang

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