Memory device and equalizing circuit for memory device

Details Memory device and equalizing circuit for memory device Memory device and equalizing circuit for memory device

2000-06-12

2001-08-14

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S207000, C365S222000, C365S204000

Reexamination Certificate

active

06275429

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more particularly, to an input and output line equalizing circuit which optimizes the efficiency of a layout and a memory device using the equalizing circuit.
2. Description of the Related Art
In general, semiconductor memory devices include equalizing circuits for maintaining a pair of bit lines, or a pair of input and output lines, at a certain level in order to increase data reading or writing speed. The equalizing circuit provides a certain level of voltage to the pair of bit lines, or the pair of input and output lines, via which data is transmitted and maintains the voltage levels of the pair of bit lines, or the pair of input and output lines, equal. Namely, the equalizing circuit increases the data reading or writing speed by maintaining the pair of bit lines, or the pair of input and output lines, at a certain voltage level before a data reading or writing operation is performed.
The time for precharging the pair of input and output lines using the equalizing circuit has increased due to the increase of loading and resistance of the pair of input and output lines in view of the high level of integration at memory devices.
In order to solve this problem, a method of precharging the pair of input and output lines from both ends has been recently provided. Namely, the pair of input and output lines are precharged from both ends by arranging the equalizing circuit at both ends of the pair of input and output lines. Accordingly, the speed at which the pair of input and output lines are precharged increases.
FIGS. 1 and 2
are circuit diagrams showing generally used conventional equalizing circuits.
FIG. 3
is a timing diagram of the main signals used for the equalizing circuits shown in
FIGS. 1 and 2
.
Referring to
FIG. 1
, an equalizing circuit
10
, which is an example of a conventional technology, is arranged between a pair of input and output lines IO and IOB and operates in response to a precharge signal IOPRGB. The equalizing circuit
10
includes an equalizing transistor
12
and precharge transistors
14
and
16
.
Referring to
FIG. 2
, an equalizing circuit
20
, which is another example of a conventional technology, includes an equalizer
22
arranged between the pair of input and output lines IO and IOB and an equalization control circuit
24
for controlling the equalizer
22
. The equalization control circuit
24
includes a NAND gate
26
and an inverter
28
and operates in response to a sensing enable signal LANG and a precharge signal IOPRGB.
The conventional equalizing circuits
10
and
20
are enabled in response to the activation of the precharge signal IOPRGB during an interval in which the sensing enable signal LANG is activated, thus precharging the pair of input and output lines IO and IOB to a predetermined voltage level, for example, a Vcc level, as shown in FIG.
3
.
When the conventional equalizing circuits
10
and
20
as shown in
FIGS. 1 and 2
are arranged at both ends of the pair of input and output lines IO and IOB, it is possible to reduce the time for restoring the voltage level of the pair of input and output lines to the Vcc level by increasing the speed at which the pair of input and output lines are precharged.
However, when the equalizing circuits
10
and
20
are arranged at both ends of the pair of input and output lines IO and IOB in order to increase the precharge speed, the required layout area is larger than when the equalizing circuits
10
and
20
are arranged at only one end of the pair of input and output lines. In particular, since the NAND gate
26
included in the equalizing circuit
20
shown in
FIG. 2
is driven by an internal supply voltage Vcc level, an internal supply voltage supply line must be additionally provided in the peripheral circuit where the equalizing circuit
20
is arranged. Since devices used in the peripheral circuits are generally driven by an external supply voltage, the interial supply voltage supply line is only required for driving the NAND gate
26
. Therefore, when the conventional equalizing circuits
10
and
20
are arranged at both ends of the pair of input and output lines, it is possible to increase the precharge speed, however, the required layout area increases.
SUMMARY OF THE INVENTION
To solve the above problem, the present invention provides an input and output line equalizing circuit capable of increasing precharge speed without increasing the required layout area.
The present invention also provides a memory device using the above equalizing circuit.
According to one embodiment of the present invention, an equalizing circuit is provided for connection to a pair of input and output lines of a memory device, the equalizing circuit comprising: an equalization control circuit for providing at an output terminal a precharge signal in response to activation of a first or a second equalization signal; and an equalizing unit having a control terminal coupled to the output terminal of the equalization control circuit, the equalizing unit being connected to the pair of input and output lines, for maintaining the pair of input and output lines at the same voltage level.
According to one aspect of the present invention, in an equalizing circuit of the first embodiment, the equalization control circuit, comprises: a first transmission gate having an input terminal for receiving a precharge signal and an output terminal for outputting the precharge signal in response to the activation of the first equalization signal; and a second transmission gate having input and output terminals commonly connected to the input and output terminals of the first transmission gate, the second transmission gate outputting the precharge signal in response to the activation of the second equalization signal.
According to another embodiment, a memory device is provided which includes first and second memory blocks and a pair of input and output lines which are shared by the first and second memory blocks, the memory device comprising: first and second bitline precharge circuits for precharging to a predetermined voltage a first and a second pair of bitlines associated with the first and second memory blocks respectively; first and second bitline sense amplifiers associated respectively with the first and second pair of bitlines for sensing and amplifying data on the pairs of bitlines; a first and a second block selection switch associated respectively with said first and second memory blocks, and a first and a second column selection gate associated respectively with said first and second memory blocks for connecting a selected pair of bitlines of a selected memory block to the pair of input and output lines; a first equalizing circuit coupled to the pair of input and output lines at a first location; and a second equalizing circuit coupled to the pair of input and output lines at a second location spaced apart from said first location.
According to another aspect of the present invention, in the immediately preceding embodiment, the first equalizing circuit comprises: an equalization control circuit for providing at an output terminal a precharge signal in response to activation of a first or a second equalization signal; and an equalizing unit having a control terminal coupled to the output terminal of the equalization control circuit, the equalizing unit being connected to the pair of input and output lines, for maintaining the pair of input and output less at the same voltage level.
According to the present invention, it is possible to improve the layout efficiency of the peripheral circuit since it is not necessary to additionally provide the internal supply voltage supply line.


REFERENCES:
patent: 5623446 (1997-04-01), Hisada et al.
patent: 5657282 (1997-08-01), Lee
patent: 5734619 (1998-03-01), Numata et al.
patent: 5970006 (1999-10-01), Numata et al.
patent: 6014662 (2000-08-01), Kim et al.
patent: 6108254 (2000-08-01), Watanabe et al.
patent: 6128238 (2000-10-01), Nagai et al.

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