Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-06-26
2007-06-26
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S763000, C714S773000
Reexamination Certificate
active
10193319
ABSTRACT:
When to a memory cell array21a read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into memory units31to37each of which has four bits which are arranged along a direction of a word line. On writing the 7-bit data in the memory cell array, bits of the 7-bit data that are different from one another are written as written bit data along the direction of the word line in the memory units31to37, respectively. In the 7-bit data, the written bit data has an interval of four bits. Error correcting circuits performs an error correction of the 7-bit data in each of the 7-bit data.
REFERENCES:
patent: 4618943 (1986-10-01), Aipperspach et al.
patent: 4665537 (1987-05-01), Moriyama
patent: 5450424 (1995-09-01), Okugaki et al.
patent: 5671239 (1997-09-01), Higashitani et al.
patent: 5862097 (1999-01-01), Toda
patent: 5991201 (1999-11-01), Kuo et al.
patent: 6065146 (2000-05-01), Bosshart
patent: 6223322 (2001-04-01), Michigami et al.
patent: 6785835 (2004-08-01), MacLaren et al.
patent: 1278647 (2001-01-01), None
patent: 07-045095 (1995-02-01), None
patent: 388009 (2001-04-01), None
patent: WO 01/02959 (2001-01-01), None
patent: WO 01/02959 (2002-01-01), None
Kiyohiro Furutani et al., “A Built-In Hamming Code ECC Circuit for DRAM's”, IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 50-56.
Hyungsoon Shin, “Modeling of Alpha-Particle-Induced Soft Error Rate in DRAM”, IEEE Transactions of Electron Devices, vol. 46, No. 9, Sep. 1999, pp. 1850-1857.
Fujino Takeshi
Hatakenaka Makoto
Mangyo Atsuo
Nii Koji
Lamarre Guy
Nguyen Steve
Renesas Technology Corp.
LandOfFree
Memory circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3850055