Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
1998-02-27
2001-02-06
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S801000
Reexamination Certificate
active
06185718
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to a memory system providing parity detecting capabilities for non-parity computer systems.
BACKGROUND OF THE INVENTION
The integrity requirements for personal computer systems have grown rapidly in the past few years. At the present time, newer operating systems and applications require a great deal of memory. Also, the amount of memory which can be accommodated in personal computer systems continues to increase rapidly. Such personal computer systems have in the past typically been provided only with the capability of writing and checking parity with many recent systems altogether eliminating parity. Computer memory comes in two basic forms: Random Access Memory (hereinafter RAM) and Read-Only Memory (hereinafter ROM). RAM is generally used by a processor for reading and writing data. ROM is generally used for storing data which will never change, such as the Basic Input/Output System (hereinafter BIOS).
Generally, RAM makes up the bulk of the computer system's memory, excluding the computer system's hard-drive, if one exists. RAM typically comes in the form of dynamic RAM (hereinafter DRAM) which requires frequent recharging or refreshing to preserve its contents. Organizationally, data is typically arranged in bytes of 8 data bits. An optional 9th bit, a parity bit, acts as a check on the correctness of the values of the other eight bits. Within a computer system, it is important that data transmitted between the central processing unit, “CPU” and the memory is being transferred accurately. In order to ensure that data transmission is error free, a data transmission attribute known as parity may be used. Data is grouped together in
8
bit chunks called bytes. Error detection methods such as parity add additional data bits in order to verify if the data byte has been transmitted intact. With parity, an additional data bit, called a parity bit, is generated and added onto each data byte. The parity bit may be set to a 1 or 0 depending on the number of 1 data bits found in the byte. If even parity is selected, the parity bit that is added will make the total number of “1” bits in the byte equal an even number. However, if odd parity is selected, the parity bit that is added will make the total of “1” bits in the byte equal an odd number. In the case of either “even” or “odd” parity, if a memory bit is corrupted, the bad parity condition will be flagged, and generally, the system will crash when the error is detected. In the case of systems which do not write and check parity, corrupted data can cause malfunction of the system. Moreover, with the advent of large applications which normally require large amounts of memory, these are the most exposed to such crash and data corruption.
Many personal computers have the feature that additional memory can be added to the computer system. Typically, Dynamic Random Access Memory (“DRAM”) can be added by a user who requires additional storage. A popular device for accomplishing an addition of DRAM is a memory card known as a Single Inline Memory Module (“SIMM”). A SIMM (Single Inline Memory Module) is a printed circuit board having, among other things, memory chips and connection points or pins. SIMMs are inserted into special sockets on the computer system's motherboard or memory carrier card. A central characteristic of SIMMs is that although there are connection pins on both sides of the SIMM's printed circuit board, these connections are not singular. That is, pin
1
on the front side of the printed circuit board is connected to pin
1
on the backside of the printed circuit board. Therefore, although most SIMMs have a total of 144 pins, only 72 are available for electrical connection.
A DIMM (Dual Inline Memory Module) is also a printed circuit board having, among other things, memory chips and connection points or pins. DIMMs are also inserted into special sockets on the computer system's motherboard or memory carrier card. However, the DIMM includes a dual row of contacts, one on each side of the printed circuit board, which are available for electrical contact. Most general DIMMs include a total of 168 pins, with 84 pins on the front side and 84 pins on the back side of the printed circuit board. Each pin is available for electrical contact.
Many computer systems do not provide means for error detection. Also, many of today's memory modules do not store parity bits. DRAM memory cards in non-parity systems can fail with no indication of where the problem is located being given to the operator. In other words, a DRAM on a SIMM or DIMM could fail, and the operator would be unable to determine which DRAM on the memory module is responsible for the failure. This failure of memory cards in a non-parity system can potentially create errors in operation, can cause system lock-up or both. Currently, a common solution when operation errors or system lock-up occur is to swap the entire system memory for a new system memory. This approach is wasteful and expensive, but since memory card failures are a primary source of computer system failures, it is quicker to swap an entire failed memory with a new memory than to systematically examine and determine which memory card in the memory system is causing the problem.
Furthermore, the typical memory chip has a 4, 8 or 16 bit wide data field. To add parity, such a system must use either a x9 chip or two x4 chips plus a x1 chip or any such equivalent of a x9 chip or x1 chip such as a quad CAS chip added as an extra chip. In an effort to reduce the number of chips needed for a computer system—which reduces cost, the extra chip required for parity is eliminated. Accordingly, SIMMs designed to accommodate a parity system are difficult to find, if not totally unavailable. Therefore, current systems can neither generate nor check parity, and the entire memory must be replaced when memory cards fail. Thus, a need exists for inline memory modules which accommodate parity and provide for indication of a failed module.
Due to the importance of insuring data is accurately transmitted between the CPU of a computer system and the system's memory, techniques other than parity can be used to ensure that data transmission is error free. One such technique is error correction code (“ECC”). ECC is similar to parity in that ECC takes the existing data and generates a special series of bits which code for what the data byte should be. In a system utilizing ECC, both single bit errors and double bit errors are detected. Furthermore, beyond merely detecting the errors as in a parity system, ECC can correct the errors during data transmission. Typically, ECC circuitry and logic is provided in the motherboard of a computer system, but many computer systems do not have ECC capabilities. Thus, a need exists for inline memory modules which generate ECC for non-ECC systems.
SUMMARY OF THE INVENTION
According to the present invention, a computer system and method of using the same is provided in which a memory card design adds parity error detecting capability to non-parity systems. The system includes SIMM or DIMM memory cards in which logic for generating and storing parity bits is provided along with a technique for indicating which module has failed. In one DIMM embodiment, controlling and decoding an error indicator to an EPROM is provided. Thus, while non-parity is becoming standard, the associated difficulties in detecting problems in memory cards is eliminated by logic for generating and storing parity. Also, logic is provided for controlling and decoding an error indicator to an EPROM in such embodiment. An indicator for indicating on which memory card the error occurred is provided.
In another embodiment, an inline memory module is provided with logic for generating error correction code in a non-error-correction code system. Furthermore, the data bits are checked against the check bits and corrected if an error occurred. In one embodiment a set of exclusive or (“XOR”) gates are utilized to check and correct the data bits
Dell Timothy J.
Dimitri Kamal E.
Dramstad Kent A.
Faucher Marc R.
Hazelzet Bruce G.
Cady Albert De
Hogg William N.
International Business Machines - Corporation
Ton David
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