Memory architecture using new power saving row decode implementa

Details Memory architecture using new power saving row decode implementa Memory architecture using new power saving row decode implementa

1994-09-29

1996-05-21

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Multiplexing

36523003, 36523004, 36523005, 365 63, G11C 700

Patent

active

055196551

ABSTRACT:
The invention disclosed herein comprises a memory architecture using a new power saving ROW decode implementation. The new power saving ROW decode implementation uses a built in column mux of two. Two ROW drivers are provided for each ROW address. Each row signal from an individual ROW driver connects to every other memory cell (10). An individual ROW driver is selected based on the select signals used in the column mux. Being that the ROW drivers are muxed along with the columns, only memory cells of interest are selected. All unselected memory cell bit lines remain precharged from the previous precharge cycle thus reducing precharge power consumption as compared with previous memory architectures.

REFERENCES:
patent: 5089992 (1992-02-01), Shinohara
patent: 5197035 (1993-03-01), Ito
patent: 5276650 (1994-01-01), Kubota
patent: 5291443 (1994-03-01), Lim

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