Masked-gate MOS S/D implantation

Details Masked-gate MOS S/D implantation Masked-gate MOS S/D implantation

1996-07-15

1997-12-23

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438551, H01L 218238

Patent

active

057007292

ABSTRACT:
The problem of how to prevent trapping charge during high energy ion implantation, as part of a PLDD, NLDD, PS/D, and NS/D manufacturing process, has been solved through use of a protective cap of photoresist which is applied to the gate prior to the high energy ion implantation. Said protective cap is readily removed after ion implantation.

REFERENCES:
patent: 5200028 (1993-04-01), Tatsumi
patent: 5354700 (1994-10-01), Huang et al.
patent: 5385857 (1995-01-01), Solo de Zaldivar
patent: 5393682 (1995-02-01), Liu
patent: 5534449 (1996-07-01), Dennison et al.

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