Mask ROM and method of fabricating the same

Details Mask ROM and method of fabricating the same Mask ROM and method of fabricating the same

2007-06-27

2009-12-29

Lindsay, Jr., Walter L (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S328000, C438S637000, C438S778000, C257S390000, C257SE21662, C257SE21667

Reexamination Certificate

active

07638387

ABSTRACT:
A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.

REFERENCES:
patent: 6731535 (2004-05-01), Ooishi et al.
patent: 2005/0073010 (2005-04-01), Lai et al.
patent: 2008/0128853 (2008-06-01), Choi et al.
Japanese Patent Publication No. JP6334139 to Masataka et al., having Publication date of Dec. 12, 1994 (w/English Abstract page).
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Korean Patent Application No. 1020030030184 to Shin, having Publication date of Nov. 20, 2004 (w/ English Abstract page).
Japanese Patent Application No. 07-335578 to Nobufumi et al., having Publication date of Sep. 13, 1996 (w/ English Abstract page).
Japanese Patent Application No. 2004-075768 to Koichi, having Publication date of Sep. 29, 2005 (w/ English Abstract page).

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