Manufacturing of cavity fuses on gate conductor level

Details Manufacturing of cavity fuses on gate conductor level Manufacturing of cavity fuses on gate conductor level

1999-03-31

2001-08-14

Fabury, Jr., Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S333000, C438S589000

Reexamination Certificate

active

06274440

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to fuses within semiconductor devices and more particularly to an improved method of forming a structure having a cavity around a gate stack conductor fuse.
2. Description of the Related Art
Semiconductor integrated circuits (IC) and their manufacturing techniques are well known. In a typical integrated circuit, a large number of semiconductor devices may be fabricated on a silicon substrate. To achieve the desired functionality, a plurality of conductors are typically provided to couple selected devices together. In some integrated circuits, conductive links are coupled to fuses, which may be cut or blown after fabrication using lasers or excessive current/voltage.
In a dynamic random access memory (DRAM) circuit, for example, fuses may be employed during manufacturing to protect some of the transistors' gate stacks from destruction due to inadvertent built-up of charges. Once fabrication of the IC is substantially complete, the fuses may be blown or cut to permit the DRAM circuit to function as if the protective current paths never existed.
Fusible links generally comprise metal lines that can be explosively fused open by application of excessive energy which causes a portion of the link material to vaporize and a portion to melt. Typically, the fusible link is thin and is made of aluminum or polysilicon. Alternatively, the fuse link may be made of the same metals as the chip conductors.
The increasing speed requirements of logic chips are the driving force behind these fusible link materials. More commonly, fuses may be employed to set the enable bit and the address bits of a redundant array element in a DRAM circuit.
FIG. 1
illustrates a typical dynamic random access memory integrated circuit, having a main memory array
102
. To facilitate replacement of a defective main array element within the main memory array
102
, a redundant array
104
is provided as shown. A plurality of fuses in a fuse array
106
are coupled to redundant array
104
via a fuse latch array
108
and a fuse decoder circuit
110
. To replace a defective main memory array element, individual fuses in the fuse array
106
may be blown or cut to set their values to either a “1” or a “0” as required by the decoder circuit.
During operation, the values of the fuses in the fuse array
106
are typically loaded into a fuse latch array
108
upon power up. These values are then decoded by fuse decoder circuit
110
during run time, thereby facilitating the replacement of specific failed main memory array elements with specific redundant elements of redundant array
104
. Techniques for replacing failed main memory array elements with redundant array elements are well known in the art and will not be discussed in great detail herein.
As mentioned above, the fuse links within the fuse array
106
may be selectively blown or cut with a laser beam or excess current/voltage. Once blown the fuse changes from a highly conductive state to a highly resistive (i.e., non-conductive) state. A blown fuse inhibits current from flowing through and represents an open circuit to the current path. With reference to
FIG. 2A
, fuse links
202
,
204
,
206
, and
208
of the fuse array element
106
are shown in their unblown (i.e., conductive) state. In
FIG. 2B
, fuse link
204
has been blown (“opened”), thereby inhibiting the flow of current therethrough.
However, if the fuse link material is not sufficiently dispersed within the surrounding area, the fuse link may still represents a conductive path even after it is theoretically blown. In other words, especially with electrically blown fuses, the fuse blow is sometimes unreliable. Therefore, cavities or areas of adsorption material are often placed adjacent the fuse link material to provide a location for the melted and vaporized material to disburse.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.
The anisotropical etching is preferably a dry etch and the isotropical etching is preferably a wet etch. Further, the isotropic etching etches the oxide layers at a faster rate than it etches the semiconductor substrate, the gate conductor stack, the first conductive material or the second conductive material. Thus, the cavity is bounded by the semiconductor substrate, the first conductive material and the second conductive material. In other words, isotropic etching forms the cavity to completely surround the gate conductor stack, such that the gate conductor stack is suspended from one portion of the semiconductor substrate to another portion of the semiconductor substrate within the cavity.
After the isotropic etching, an insulator is deposited over the second conductive layer to seal the etching holes. In addition, the oxide layers may be layers of BPSG and/or TEOS. Also, the first conductor may be polysilicon and the second conductor may be tungsten.
Another embodiment of the invention is a method for forming a fuse and includes forming a fuse element on a substrate, forming at least one insulator on the substrate and the conductor, forming a seal above the insulator, forming at least one opening through the seal and the insulator; and etching the insulator through the opening to form a cavity adjacent the fuse element, where the cavity is bounded by the substrate and the seal.
The method may also include forming at least one contact opening in the insulator and filling the contact opening with a conductor such that the conductor makes electrical contact with the fuse element. The forming of the seal includes forming a patterned conductive layer over the insulator, such that the patterned conductive layer is electrically connected to the conductor. The conductor and the patterned conductive layer make up the seal. Thus, the substrate and the seal combine to surround the fuse element, such that the etching leaves the substrate and the seal to form the cavity.
The fuse element may be a gate conductor over a shallow trench isolation region within the substrate. The etching removes the shallow trench isolation region and forms the cavity to completely surround the gate conductor, such that the gate conductor is suspended from one portion of the substrate to another portion of the substrate within the cavity.
The forming of the opening comprises a dry etch and the etching of the insulator comprises an wet etch. The etching etches the insulator at a faster rate than it etches the substrate, the fuse element or the seal, such that the cavity is bounded by the substrate and the seal. After the etching, a second insulator is deposited over the seal to seal the opening.
Another embodiment of the invention is a fuse structure that includes a substrate, a gate conductor stack above the substrate, at least one conductive contact on the substrate, a conductive pattern above the gate conductor stack and connected to the conductive contact and a cavity s

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