Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-15
2003-01-07
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S201000, C438S258000, C438S981000
Reexamination Certificate
active
06503800
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and more particularly to a manufacturing method of a semiconductor device, for limiting: the film thicknesses of gate thermal oxide films of a plurality of processing circuit portions comprising MOS-transistors; and the film-thickness-difference variation among gate thermal oxide films of the processing circuits comprising the MOS-transistors; within desired ranges without deteriorating the performance of the MOS-transistors.
2. Description of the Prior Art
Those semiconductor devices such as represented by LSI's and VLSI's have been developed year by year, concerning increased density, increased integration, enhanced function, and increased processing speed. Achieving increased density of semiconductor devices requires precise structures thereof. Further, achieving increased integration and higher function requires that: (i) different kinds of devices (or circuits) such as processing devices and (ii) semiconductor memory devices (such as non-volatile memory devices), which have been inherently manufactured independently, are to be brought into semiconductor devices collectively mounted on a single plate of semiconductor substrate. Moreover, achieving an increased processing speed requires to reduce the thickness of gate thermal oxide films of MOS-transistors (MOSFET's).
However, excessively reduced thickness of gate thermal oxide films causes such a phenomenon that electric current (gate leak electric current) flows from a gate electrode to a source electrode or from a gate electrode to a sub-electrode. This phenomenon causes increased power consumption.
Such as in mobile telephones (portable telephones, PHS's) and household electric appliances, those semiconductor devices to be adopted are required to have such characteristics: to execute faster arithmetic processing in operation; and to have reduced power consumption on stand-by. Since the faster arithmetic processing means or requires increased power consumption, there are required conflicting performances for a single semiconductor device.
FIG. 25
shows a semiconductor device having a structure coping with the conflicting requirements in operation and on stand-by.
Reference numeral
100
designates a semiconductor device constituted of a first processing circuit portion Q
1
which operates or works in operation, a second processing circuit portion Q
2
which operates on stand-by, and other circuit portion Q
3
. The first processing circuit portion Q
1
has a thinned gate thermal oxide film for enabling a high-speed processing calculation, and the second processing circuit portion Q
2
has a thickened gate thermal oxide film for reduced power consumption. For example, both of the gate thermal oxide films of the first processing circuit portion Q
1
and second processing circuit portion Q
2
are to be preferably deposited to exceed 10 angstroms, at a precision of several angstroms relative to a desired value, and without variance.
Japanese Patent Application Laid-Open No. HEI-2-129968 (129968/1990) discloses a method for implementing those circuit portions within a single semiconductor device which are driven by a plurality of types of power supply voltages, and for differently forming the thicknesses of the gate thermal oxide films of such circuit portions. This manufacturing method shall be detailed hereinafter.
FIGS. 26 through 36
show a conventional manufacturing method of semiconductor devices.
As firstly shown in
FIG. 26
, there are formed: element-separating insulation films
102
on a one-conductive type of semiconductor substrate
101
; a p-type well region
103
in a semiconductor element forming region (hereinafter called “element forming region”) of a first processing circuit portion Q
1
n; a p-type well region
104
in an element forming region of a second processing circuit portion Q
2
n; and a p-type well region
105
of a non-volatile memory circuit portion (hereinafter called “memory circuit portion”) Qm.
Next, as shown in
FIG. 27
, there is grown a first gate thermal oxide film
106
so as to have a thickness of 50 angstroms to 100 angstroms over the whole surface of the semiconductor substrate
101
, and then there is formed a first conducting layer
107
over the whole surface of the semiconductor substrate
101
including the first gate thermal oxide film
106
. The first conducting layer
107
can be formed such as by growing a polycrystalline silicon film deposited by a CVD (Chemical Vapor Deposition) method. Next, as shown in
FIG. 28
, the first conducting layer
107
is patterned into a predetermined shape of first conducting layer
107
a.
This first conducting layer
107
a
is left in the element forming region of the memory circuit portion Qm only.
Next, as shown in
FIG. 28
, there is grown an insulating film
108
over the respective surfaces of the first gate thermal oxide film
106
and first conducting layer
107
a.
This insulating film
108
has a three-layer structure comprising an oxide film, a nitride film and another oxide film such as deposited by a CVD method, and generally called “ONO film”.
Next, as shown in
FIG. 30
, the first gate thermal oxide film
106
and insulating film
108
are patterned into predetermined shapes of first gate thermal oxide film
106
a
and insulating film
108
a,
respectively. The first gate thermal oxide film
106
a
and insulating film
108
a
are formed to leave the element forming region of the memory circuit portion Qm. At this time, the shape of the first conducting layer
107
a
is unchanged, since it is covered by the insulating, film
108
a.
Next, as shown in
FIG. 31
, there is provided a second gate thermal oxide film
109
over the whole surfaces of the element forming regions of the first processing circuit portion Q
1
n and second processing circuit portion Q
2
n. This second gate thermal oxide film
109
is rendered to grow into a thickness of 15 to 20 angstroms in the element forming regions. At this time, no second gate thermal oxide films
109
are formed on the insulating film
108
a
of the memory circuit portion Qm, because of the nature of the ONO film.
Next, as shown in
FIG. 32
, the second gate thermal oxide film
109
is patterned into a predetermined shape
109
a.
This second gate thermal oxide film
109
a
is left in the element forming region of the second processing circuit portion Q
2
n only.
Next, as shown in
FIG. 33
, there is grown a third gate thermal oxide film
110
over the element forming regions of the first processing circuit portion Q
1
n and second processing circuit portion Q
2
n, such that the third gate thermal oxide film
110
has a thickness between 15 angstroms exclusive to 22 angstroms inclusive in the element forming region of the first processing circuit portion Q
1
n. At this time, no third gate thermal oxide films are formed on the insulating film
108
a
of the memory circuit portion Qm because of the nature of the ONO film, whereas the second gate thermal oxide film
109
a
in the second processing circuit portion Q
2
n is further deposited so that the thickness exceeds 25 angstroms and reaches 32 angstroms. Further, the shape of the second gate thermal oxide film
109
a
is also integrated with the third gate thermal oxide film. Thus, the thermal oxide film in the second processing circuit portion Q
2
n shall be called a “third gate thermal oxide film
110
a”.
Next, as shown in
FIG. 34
, there is formed a second conducting layer
111
over the third gate thermal oxide film
110
, third gate thermal oxide film
110
a
and insulating film
108
a.
The second conducting layer
111
is formed in the same manner as the first conducting layer
107
, such as by growing a polycrystalline silicon film deposited by a CVD (Chemical Vapor Deposition) method.
Next, as shown in
FIG. 35
, the first gate thermal oxide film
106
a,
first conducting layer
107
a,
insulating film
108
a,
third gate thermal oxide film
110
and third gate thermal o
Goto Yoshiro
Toda Takeshi
Chaudhari Chandra
Chen Jack
Katten Muchin Zavis & Rosenman
NEC Corporation
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