Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-05-24
2011-05-24
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S744000
Reexamination Certificate
active
07949917
ABSTRACT:
A system comprises storage that includes first and second data. The system also comprises circuit logic coupled to the storage. The circuit logic receives a plurality of clock signals. As a result of receiving a signal, the circuit logic uses the plurality of clock signals to obtain the first and second data and to provide the first and second data to target logic coupled to the circuit logic. The system resets the circuit logic between providing the first data and providing the second data.
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Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors.Lebeck, A.R. ; Wood, D.A. ; Jun. 22-24, 1995.
Brady W. James
Gaffin Jeffrey A
Merant Guerrier
Pessetto John R.
Telecky , Jr. Frederick J.
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