Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-04-01
2000-08-15
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714726, G01R 328
Patent
active
06105156&
ABSTRACT:
An LSI tester having a path analysis means for tracing a series of connections reversely along a designated signal flow path from one of flip-flops of DUT (device under test) at which flip-flop an inconsistency in pattern value has been detected as a consistency detection point by an output pattern comparator, based on circuit information in DUT, and for identifying firstly reachable flip-flops or external terminals from the inconsistency detection point as arrival points. And a sequence-pattern-inverting means sequentially inverts at least partly the values of successive test patterns one at a time with respect to each of the arrival points. The fault position in DUT is narrowed down from the arrival points simply in a shorter time.
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Cady Albert De
Lamarre Guy
NEC Corporation
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