Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
2002-02-13
2002-10-08
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S680000, C438S758000, C438S761000, C427S248100, C427S585000
Reexamination Certificate
active
06461979
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the enhancement of Low Pressure Chemical Vapor Deposition (LPCVD).
(2) Description of the related Prior Art
The process of Chemical Vapor Deposition (CVD) is widely applied and well known in the art of creating semiconductor devices and it explained in detail in for instance the text Silicon Processing for the VLSI Era, Volume 1, by Stanley Wolf and Rickard N. Tauber, published by the Lattice Press. From this source the process and its salient features are briefly highlighted.
The CVD process can be summarized as consisting of the following sequence of steps:
a given composition and flow rate of reactant gasses and diluent inert gasses is introduced into a reaction chamber
the gas species move to the substrate
the reactants are absorbed on the substrate
the adatoms undergo migration and film-forming chemical reactions, and
the gaseous by-products of the reaction are de-sorbed and removed from the reaction chamber.
Energy to drive the reactions can be supplied by several methods such as thermal, photons or electrons, with thermal energy being the most frequently form of energy.
In practice, the chemical reactions of the reactant gasses leading to the formation of a solid material may take place not only on or very close to the surface of the wafers a so-called heterogeneous reaction, but can also take place in the gas phase, a so-called homogeneous reaction. Heterogeneous reactions are much more desirable since such reactions occur selectively only on heated surfaces and are known to produce good quality films of semiconductor material. Homogeneous reactions in the other hand are undesirable since these reactions form gas phase clusters of the depositing material, which can result in poorly adhering, low density films or in defects in the depositing film. In addition, such reactions also consume reactants and can cause a decrease in deposition rates. Thus, one important characteristic of a CVD process is the degree to which heterogeneous reactions are favored over gas phase reactions.
One of the key aspects and concerns of applying CVD processes is the uniformity with which the semiconductor material is deposited over the surface of a wafer, a concern that is further emphasized by the increased size of semiconductor wafers that are being used for the creation of semiconductor devices. A value of concentration gradient can be used in this respect, which is indicative of the amount of semiconductor material that is deposited over a unit of surface. Because of the impact of the concentration gradient, it has been found that the semiconductor material is deposited thinner in the center of the wafer than the average of the deposition thickness over the complete surface of the wafer. For the same reason, it has been found that the deposited material is thicker around the perimeter of the wafer than the average of the deposition thickness over the surface of the wafer. The variation of the concentration gradient of the deposition across the surface of a wafer leads to poor uniformity of the deposited material across the surface of the substrate.
Extreme uniformity of the deposited material over a semiconductor surface is required in order to achieve uniformity of the devices that are created using the entire surface of the wafer. With increased wafer size, this uniformity is more difficult to achieve and to maintain. The invention provides a method that addresses this concern.
U.S. Pat. No. 4,992,044 (Pillipossian) shows an LPCVD furnace with improved within wafer uniformity.
U.S. Pat. No. 5,976,990 (Mercaldi et al.) discloses a LPCVD SiN process.
U.S. Pat. No. 4,851,370 (Doklan et al.) shows a LPCVD SiN process.
U.S. Pat. No. 4,888,142 (Hayashi) and U.S. Pat. No. 4,395,438 (Chiang) are related patents.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method for enhanced uniformity of deposited layers over a semiconductor surface.
It is another objective of the invention to eliminate a temperature variation or gradient between the center of the substrate and the perimeter of the substrate during the process of CVD.
It is yet another objective of the invention to offset the conventional difference in temperature between the center of the substrate and the perimeter of the substrate during CVD processing, where conventionally the edge of the temperature will be elevated to a lower temperature than the center of the substrate.
It is a further objective of the invention to eliminate the effect that the temperature gradient has on the deposition rate of CVD deposited semiconductor material, by reducing the deposition rate of the semiconductor material when proceeding toward the perimeter of the substrate.
In accordance with the objectives of the invention a new method is provided for the application of Chemical Vapor Deposition (CVD) processes. Where conventional CVD processes are performed while maintaining one, constant temperature during the CVD process, from the start of the CVD process up to the point where the CVD process is completed, the invention provides for first raising the temperature to a processing temperature and then gradually reducing the applied temperature within the cycle time that is required for the completion of the CVD process.
REFERENCES:
patent: 4395438 (1983-07-01), Chiang
patent: 4851370 (1989-07-01), Doklan et al.
patent: 4888142 (1989-12-01), Hayashi et al.
patent: 4992044 (1991-02-01), Philipossian
patent: 5953634 (1999-09-01), Kajita et al.
patent: 5976990 (1999-11-01), Mercaldi et al.
patent: 6017351 (2000-06-01), Venkatasubramanian
patent: 6117755 (2000-09-01), Kun-Yu et al.
patent: 6350648 (2002-02-01), Ping et al.
Chen Bu-Fang
Chen Song-Fu
Lin Chih-Hao
Zhuang Xi-Sheng
Ackerman Stephen B.
Ghyka Alexander
Saile George O.
Taiwan Semiconductor Manufacturing Company
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