Low-voltage single-layer polysilicon eeprom memory cell

Details Low-voltage single-layer polysilicon eeprom memory cell Low-voltage single-layer polysilicon eeprom memory cell

2006-12-05

2006-12-05

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S157000, C438S223000, C438S238000, C438S257000, C438S323000, C257S314000, C257S315000, C257S316000, C257S318000

Reexamination Certificate

active

07144775

ABSTRACT:
The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.

REFERENCES:
patent: 5600593 (1997-02-01), Fong
patent: 5904524 (1999-05-01), Smolen
patent: 6022770 (2000-02-01), Hook et al.
patent: 6346457 (2002-02-01), Kawano
patent: 6449192 (2002-09-01), Otsuka
patent: 2005/0017285 (2005-01-01), Tzeng et al.
Wolf et al, Silicon Processing for the VLSI Era: vol. 1, Lattice Press: Sunset Beach, CA, 2000, pp. 225-226 and 830-831.

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