Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-06-07
2005-06-07
Schillinger, Laura M. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S166000, C438S655000
Reexamination Certificate
active
06902966
ABSTRACT:
A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate; forming source/drain extensions in the substrate; forming first and second sidewall spacers; implanting dopants within the substrate to form source/drain regions in the substrate adjacent to the sidewalls spacers; laser thermal annealing to activate the source/drain regions; depositing a layer of nickel over the source/drain regions; and annealing to form a nickel silicide layer disposed on the source/drain regions. The source/drain extensions and sidewall spacers are adjacent to the gate electrode. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. The annealing is at temperatures from about 350 to 500° C.
REFERENCES:
patent: 5937315 (1999-08-01), Xiang et al.
patent: 5970327 (1999-10-01), Makita et al.
patent: 5977559 (1999-11-01), Zhang et al.
patent: 5986286 (1999-11-01), Yamazaki et al.
patent: 6037204 (2000-03-01), Chang et al.
patent: 6087679 (2000-07-01), Yamazaki et al.
patent: 6093937 (2000-07-01), Yamazaki et al.
patent: 6159856 (2000-12-01), Nagano
patent: 6225197 (2001-05-01), Maekawa
patent: 6251757 (2001-06-01), Yu
patent: 6274488 (2001-08-01), Talwar et al.
patent: 6287925 (2001-09-01), Yu
patent: 6291278 (2001-09-01), Xiang et al.
patent: 6300659 (2001-10-01), Zhang et al.
patent: 6323072 (2001-11-01), Yamazaki et al.
patent: 6350677 (2002-02-01), Ko et al.
patent: 6365446 (2002-04-01), Chong et al.
patent: 6365476 (2002-04-01), Talwar et al.
patent: 6387803 (2002-05-01), Talwar et al.
patent: 6399450 (2002-06-01), Yu
patent: 6403434 (2002-06-01), Yu
patent: 6420218 (2002-07-01), Yu
Heather Banisaukas et al, “Varying implant dose rate for defect reduction in laser thermal processing”, Materials Science in Semiconductor Processing, Elsevier Science Ltd., vol. 4, No. 4, Aug. 21, pp. 339-343, ISSN: 1369-8001.
International Preliminary Examination Report dated Jan. 27, 2004 received in corresponding PCT Application No. PCT/US02/32555.
Ogle Robert B.
Paton Eric N.
Tabery Cyrus E.
Xiang Qi
Yu Bin
Advanced Micro Devices , Inc.
Schillinger Laura M.
LandOfFree
Low-temperature post-dopant activation process does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low-temperature post-dopant activation process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-temperature post-dopant activation process will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3494750