Low temperature integrated via and trench fill process and appar

Chemistry: electrical and wave energy – Processes and products – Coating – forming or etching by sputtering

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

20419217, 427250, 427252, 427566, 427584, C23C 1434

Patent

active

061396974

ABSTRACT:
The present invention relates generally to an improved process for providing complete via fill on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer, such as CVD Al or CVD Cu, is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD Cu. Next, a PVD Cu is deposited onto the previously formed CVD Cu layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD Cu layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Cu layer. The via fill process of the present invention is also successful with air-exposure between the CVD Cu and PVD Cu steps.

REFERENCES:
patent: 4784973 (1988-11-01), Stevens et al.
patent: 4920072 (1990-04-01), Keller et al.
patent: 4920073 (1990-04-01), Wei et al.
patent: 4926237 (1990-05-01), Sun et al.
patent: 4938996 (1990-07-01), Ziv et al.
patent: 4951601 (1990-08-01), Maydan et al.
patent: 4960732 (1990-10-01), Dixit et al.
patent: 4985750 (1991-01-01), Hoshino
patent: 4994410 (1991-02-01), Sun et al.
patent: 5010032 (1991-04-01), Tang et al.
patent: 5023201 (1991-06-01), Stanasolovich et al.
patent: 5028565 (1991-07-01), Chang et al.
patent: 5043299 (1991-08-01), Chang et al.
patent: 5043300 (1991-08-01), Nulman
patent: 5081064 (1992-01-01), Inoue et al.
patent: 5091339 (1992-02-01), Carey
patent: 5102826 (1992-04-01), Ohshima et al.
patent: 5102827 (1992-04-01), Chen et al.
patent: 5106781 (1992-04-01), De Vries
patent: 5143867 (1992-09-01), d'Heurle et al.
patent: 5147819 (1992-09-01), Yu et al.
patent: 5250465 (1993-10-01), Iizuka et al.
patent: 5250467 (1993-10-01), Somekh et al.
patent: 5292558 (1994-03-01), Heller et al.
patent: 5354712 (1994-10-01), Ho et al.
patent: 5380682 (1995-01-01), Edwards et al.
patent: 5439731 (1995-08-01), Li et al.
patent: 5478780 (1995-12-01), Koerner et al.
patent: 5480836 (1996-01-01), Harada et al.
patent: 5514425 (1996-05-01), Ito et al.
patent: 5585673 (1996-12-01), Joshi et al.
patent: 5607776 (1997-03-01), Mueller et al.
"CVD Aluminum for Submicron VLSI Metallization", Lai, W. Y-C., et al. Jun. 11-12, 1991.
IBM Technical Disclosure Bulletin, vol. 37, No. 10, Oct., 1994.
Nobuyoshi Awaya, Hiroshi Inokawa, Eiichi Yamamoto, Yukio Okazaki, Masayasu Miyake, Yoshinobu Arita, and Toshio Kobayashi, "Evaluation of a Copper Metallization Process and the Electrical Characteristics of Copper-Interconnected Quarter-Micron CMOS", vol. 43, No. 8, Aug., 1996, pp. 1206-1211.
K. Mikagi, H. Ishikawa, T. Usami, M. Suzuki, K. Inoue, N. Oda, S. Chikaki, I. Sakai and T. Kikkawa, "Barrier Metal Free Copper Damascene Interconnection Technology Using Atmospheric Copper Reflow and Nitrogen Doping in SiOF Film ," 1996 IEEE, pp. 365-368.
Aluminum Chemical Vapor Deposition with New Gas Phase Pretreatment Using Tetrakisdimethylamino-Titanium for Ultralarge-Scale Integrated Circuit, K. Sugai, H. Okabayashi, T. Shinzawa, S. Kishida, A. Kobayashi, T. Yako, and H. Kadokura, Jun. 16, 1995, (pp. 2115-2118).
Formation of Titanium Nitride Layers by the Nitradation of Titanium in High-Pressure Ammonium Ambient, Tohru Hara, Kouichi Tani, and Ken Inoue, Applied Physics Letters 57, Oct. 15, 1990, No. 16, New York.
Self-Aligned Titanium Silicidation by Lamp Annealing, K. Tsukamoto et al., Japanese Journal of Applied Physics Supplements, 16th Int. Conf. Solid State Devices and Materials, (1984) Koi Aug. 30-Sep. 1, Tokyo Japan, (4) pages.
Copper Metallization for ULSI and Beyond, Shyam P. Mararka and Steven W. Hymes, Critical Reviews in Solid State and Materials Sciences, 20(2):87-120 (1995).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Low temperature integrated via and trench fill process and appar does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low temperature integrated via and trench fill process and appar, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low temperature integrated via and trench fill process and appar will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2047191

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.