Low stress sidewall spacer in integrated circuit technology

Details Low stress sidewall spacer in integrated circuit technology Low stress sidewall spacer in integrated circuit technology

2006-02-28

2006-02-28

Smoot, Stephen W. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S595000, C438S682000, C438S683000

Reexamination Certificate

active

07005357

ABSTRACT:
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

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