Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-06
2001-01-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S301000, C438S592000, C438S630000, C438S649000, C438S674000, C438S682000
Reexamination Certificate
active
06180469
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor manufacturing, particularly to self-aligned silicide (silicide) technology. The present invention is particularly applicable to manufacturing ultra large scale integrated circuit (U.S.S.) Systems having features in tile deep-sub micron range.
BACKGROUND ART
Deep-submicron scaling required for ULSI Systems dominates design considerations in the micro electronics industry. As the gate electrode length is scaled down, the source and drain junctions must be scaled down accordingly, to suppress the so-called short channel effects (SCE) which degrade performance of miniaturized devices. A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance. As the source/drain junction depth (X
j
) and polycrystalline silicon line width are scaled into the deep-submicron range, parasitic series resistances of the source/drain diffusion layers and polysilicon gate electrodes increase. A conventional approach to the increase in parasitic series resistances of the source/drain diffusion layers and the polysilicon gate electrodes involves salicide technology which comprises forming a layer of titanium silicide (TiSi
2
) on the source/drain regions and gate electrode.
Conventional salicide technology employing TiSi
2
for reducing parasitic series resistance has proven problematic, particularly as design rules plunge into the deep-submicron range, e.g., about 0.18 microns and under. For example, in forming a thin TiSi
2
layer, silicide agglomeration occurs during silicide annealing to effect a phase change from the high resistivity C49 form to the low resistivity C54 form. Such agglomeration further increases the sheet resistance of the silicide film. Moreover, the formation of a thick silicide layer causes a high junction leakage current and low reliability, particularly when forming ultra shallow junctions, e.g., at an X
j
of less than about 800 Å. The formation of a thick silicide layer consumes silicon from the underlying semiconductor substrate such that the thick silicide layer approaches and even shorts the ultra-shallow junction, thereby generating a high junction leakage current.
Another problem attendant upon conventional TiSi
2
technology is the well-known increase in sheet resistance as the line width narrows. The parasitic series resistances of source/drain regions and gate electrodes are a major cause of device performance degradation and are emerging as one of the severest impediments to device scaling.
There are additional problems attendant upon conventional silicide technology employing titanium or other metals, such as cobalt, which problems are exacerbated as design rules extend into the deep-submicron range, e.g. about 0.18 microns and under. For example, conventional salicide technology for deep-submicron CMOS transistors comprises depositing a layer of metal at a predetermined thickness by physical vapor deposition (PVD), such as sputtering, over the entire wafer surface and then conducting a two step rapid thermal annealing with an intervening etching step to remove unreacted metal from the dielectric sidewall spacers on the gate electrode as well as the field isolation region. The need to remove unreacted metal from the dielectric sidewall spacers and field isolation region complicates processing and reduces manufacturing throughput as well as device reliability. In addition, as devices are scaled smaller and smaller, shorting between source/drain regions and the gate electrode becomes significant due to high temperature processing required to form low resistivity silicide layers.
There exist a need for simplified salicide technology which enables a reduction in parasitic series resistances. There exist a particular need for simplified salicide methodology in manufacturing semiconductor devices having a design rule in the deep-submicron range, e.g. a design rule less than about 0.18 microns, with increased reliability and reduced shorting between source/drain regions and the gate electrode.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a semiconductor device including a transistor comprising low resistivity contacts and exhibiting reduced parasitic series resistance and reduced leakage current.
A further advantage of the present invention is a method of manufacturing a semiconductor device having an elevated salicide structure formed with significantly reduced consumption of silicon from the underlying substrate or gate electrode.
Another advantage of the present invention is a method of manufacturing semiconductor device having a design rule less than about 0.18 microns with source/drain regions having an ultra shallow junction less than about 800 Å utilizing elevated salicide technology, thereby significantly reducing consumption of silicon from the substrate and gate electrode and, hence, avoidin, the generation of high leakage current while reducing parasitic series resistances.
Additional advantages and other features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned by practice of the present invention. The advantages of the present invention may be realized and attained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a structure comprising: a silicon-containing substrate; source/drain regions in the substrate with a channel region therebetween; a gate dielectric layer on the substrate over the channel region; a silicon-containing gate electrode, having an upper surface and side surfaces, on the gate dielectric layer; and a dielectric sidewall spacer on each side surface of the gate electrode, leaving a portion of each source/drain region exposed; selectively depositing a metal layer on the exposed portion of each source/drain region and on the upper surface of the gate electrode, with substantially no metal depositing on the dielectric sidewall spacers; forming a barrier layer within and dividing each metal layer into a lower metal portion below and an upper metal portion above the barrier layer; and heating to react the lower metal portion of each metal layer to form a metal silicide layer on the exposed portions of the source/drain regions and on the upper surface of the -ate electrode.
Another aspect of the present invention is a method of manufacturing a semiconductor device, the method comprising: forming a structure comprising a silicon-containing substrate; source/drain regions in the substrate with a channel region therebetween; a ,ate dielectric layer on the substrate over the channel region; a silicon-containing gate electrode, having an upper surface and side surfaces, on the gate dielectric layer; and a dielectric sidewall spacer on each side surface of the gate electrode, leaving a portion of each source/drain region exposed; selectively depositing a layer of nickel by electroless plating on the exposed portions of the source/drain region and on the upper surface of the gate dielectric layer; ion implanting nitrogen and annealing to form a nickel nitride barrier layer within and dividing each nickel layer into a lower nickel portion below and an upper nickel portion above the barrier layer; and heating to react the lower nickel portion of each metal layer to form a nickel silicide layer on the exposed portions of the source/drain regions and on the upper surface of the gate electrode.
A further aspect of the present invention is a semiconductor device comprising: a silicon substrate; source/drain regions in the substrate with a channel region therebetween; a gate dielectric layer on the substrate over the channel region; a silicon gate electrode, having a upper surface and side surfaces, on the gate dielectric layers; a dielectric sidewall spacer on ea
Lin Ming-Ren
Pramanick Shekhar
Xiang Qi
Advanced Micro Devices , Inc.
Hack Jonathan
Niebling John F.
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