Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant
Reexamination Certificate
2000-08-15
2001-12-04
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified encapsulant
C257S782000, C257S778000, C438S126000, C438S108000
Reexamination Certificate
active
06326700
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to a semiconductor device in which a semiconductor die mounted on a substrate is electrically coupled to external devices through arrayed conductive elements implanted on the bottom surface of the substrate.
BACKGROUND OF THE INVENTION
Ball grid array (BGA) semiconductor devices have become a mainstream package product lately because arrayed solder balls implanted on the bottom surface of a substrate to which a semiconductor die is adhered, are capable of providing increased I/O connections to the semiconductor die with external devices such as printed circuit board, when compared to conventional leadframe-based semiconductor devices. Further, the pitch between any two adjacent solder balls can be effectively reduced such that a substrate can accommodate a larger number of solder balls thereon. As a result, such BGA semiconductor device can meet the requirement in I/O connection for a high density semiconductor die.
During wire bonding of the above-mentioned conventional BGA semiconductor devices for electrically coupling the semiconductor die to the substrate onto which the semiconductor die is attached a wire bonding tool is used to first ball bond the free end of a bonding wire to a bond pad on the semiconductor die, and then stitch bond the opposite end of the bonding wire to the substrate. Right after the ball bond at the bond pad on the semiconductor die is made, the wire bonding tool is to pull the bonding wire upward to a preset height and thereafter outwardly downward to the bonding area on the substrate. This makes the top point of the wire loop formed by the bonding wire higher than the semiconductor die so that the resin encapsulant that encapsulates the semiconductor die and gold wires should have a thickness sufficient to cover the top point of the wire loop in order to prevent the bonding wires from exposure. As a result, the thickness of the encapsulated semiconductor device can not be effectively reduced.
In order to resolve the drawback in thickness of the above-mentioned conventional BGA semiconductor devices, a BGA semiconductor device with a thin profile is disclosed, as shown in FIG.
12
. This BGA semiconductor device
1
includes a substrate
11
for a semiconductor die
10
to be mounted thereon and having a hole
110
formed therewith. The hole
110
is for bonding wires
12
to pass therethrough for providing electrical connection between the semiconductor die
10
and conductive traces
111
formed on the substrate
11
. After wire bonding of the bonding wires
12
is completed, a lower encapsulant
13
is formed to encapsulate the bonding wires
12
and hole
110
. Since a part of the wire loop of the bonding wires
12
is positioned within the substrate
11
and merely another part of the wire loop of the bonding wires
12
extends beyond the bottom surface of the substrate
11
, the height h of the lower encapsulant
13
protruding from the bottom surface of the substrate
11
can be controlled to be lower than the height H of the solder balls
14
implanted on the bottom surface of the substrate
11
. Therefore, the thickness of the upper encapsulant
15
only needs to be sufficient to encapsulate the semiconductor die
10
without the consideration of the height of wire loop of the bonding wires
12
. As a result, the semiconductor device
1
is lower in height than the above-mentioned conventional BGA semiconductor device.
Although the semiconductor device
1
shown in
FIG. 12
is capable of effectively reducing the overall height, it still has the following drawbacks. First, in order to prevent the conductive traces
111
on the substrate
11
from being exposed to the atmosphere, it is necessary to provide a solder mask layer
112
on the bottom surface of the substrate
11
to completely cover the conductive traces
111
. The application of the solder mask layer
112
thus increases the cost for making the substrate
11
. Also, the use of solder mask layer
112
results in hygroscopicity concern and to cope with this problem the cost for the manufacture of the substrate
11
further increases. Further, the semiconductor device
1
is of a low profile such that, when being mounted by conventional methods such as surface mounting technology to external devices such as printed circuit board, the semiconductor device
1
tends to warp as the coefficient of thermal expansion of the substrate
11
is different from that of the upper encapsulant
15
. Warpage of the semiconductor device
1
accordingly causes the semiconductor die
10
to delaminate from the substrate
11
and adversely affect the electrical connection with external devices.
Moreover, to avoid warpage from occurrence the thickness of the substrate
11
may be increased to resist thermal stress; nevertheless this not only increases the cost of the substrate
11
but also increases the overall height. Meanwhile, during electrical performance testing of the semiconductor device
1
, the tips of testing probes (not shown) do not usually have complete contact with the solder balls
14
as the lower ends of the solder balls
14
are spherical in contour. When the contact of the testing probes with the solder balls is incomplete, the test result is accordingly misleading. Besides, the semiconductor device
1
requires expensive ball-implantation machines to implant solder balls
14
, making the overall packaging cost difficult to be reduced. Also, after the solder balls
14
are implanted onto the substrate
11
the planarity of the bottom ends of solder balls
14
is difficult to maintain, thus resulting in poor quality of the electrical connection between the semiconductor device
1
and the external device.
SUMMERY OF THE INVENTION
It is therefore an objective of this invention to provide a low-profile semiconductor device that its overall thickness can be effectively reduced.
Another objective of this invention is to provide a low-profile semiconductor device that the thickness of and the cost for making the substrate of the semiconductor device can be reduced.
Still another objective of this invention is to provide a low-profile semiconductor device that the substrate of the semiconductor device needs not be coated with solder mask, thus reducing the cost for making the substrate.
Yet another objective of this invention is to provide a low-profile semiconductor device, which can eliminate warpage of the semiconductor device such that the occurrence of delamination between the semiconductor die and the substrate can be effectively prevented.
Still another objective of this invention is to provide a low-profile semiconductor device, which can improve the accuracy of testing of electrical performance.
Yet another objective of this invention is to provide a low-profile semiconductor device, which can be electrically connected to an external device in a quality-assured way than the prior art.
In accordance with the foregoing and other objectives, the present invention proposes a novel low-profile semiconductor device. The semiconductor device comprises a substrate having a base layer and a plurality of conductive traces formed on the base layer; a semiconductor die with an active surface and an opposing inactive surface and being mounted on the base layer of the substrate via the active surface; a plurality of first conductive elements that pass through at least a hole formed in the base layer of the substrate for electrically coupling the semiconductor die to the conductive traces on the substrate; a plurality of arrayed second conductive elements arranged on and bonded to the terminal of each conductive trace for providing externally electrical connection to the semiconductor die; a first encapsulant formed on the surface of the substrate on which the semiconductor die is mounted, so as to encapsulate the semiconductor die; and a second encapsulant formed on the surface of the substrate on which the conductive traces are arrayed, so as to completely encapsulate the conductive traces,
Bai Jinchuan
Tsai Chung-Che
Anderson Kill & Olick P.C.
Clark Sheila V.
United Test Center Inc.
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