Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-02-06
2002-11-26
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S723000, C257S724000
Reexamination Certificate
active
06486546
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention: This invention relates generally to semiconductor device assemblies having molded housings. More particularly, the invention relates to connectors for joining a stack of packaged devices into a small multi-IC chip assembly package operable at high speeds.
Description of the Related Art: The evolution of the computer has resulted in a requirement for greatly increased memory capacity in much smaller packages. Another requirement is the capability for reliable operation at much higher clock speeds, e.g. up to 800 MHZ or more. In addition, the memory device(s) must be readily produced in high quantity and at low cost with reduced rates of failure or rejection. One way to provide a greater memory storage capacity in a smaller space is by stacking a plurality of memory chips and interconnecting them to produce a limited number of connections to e.g. a circuit board. In so doing, a number of factors must be addressed, including heat dissipation, ease of interconnection, impedance effects, etc.
Combining two or more semiconductor dice or chips in a single semiconductor device assembly has been used to reduce the space required for integrated circuits. Such devices are generally known as multi-chip modules (MCM). In one form, dice are stacked vertically on opposite sides of a substrate, for example, or atop each other with intervening insulative layers, prior to encapsulation. Examples of such devices are shown in U.S. Pat. No. 5,239,198 to Lin et al., U.S. Pat. No. 5,323,060 to Fogal et al. and U.S. Pat. No. 5,495,398 to Takiar et al.
U.S. Pat. No. 5,604,377 discloses a rack with multiple shelves for holding unpackaged chips. The chips are electrically connected by lead frames to a wiring interface on a vertical circuit board which can be connected to a PCB. The entire assembly is contained in a sealed enclosure.
In U.S. Pat. No. 5,602,420 to Ogata et al., multiple unpackaged dice having peripheral bond pads are spacedly stacked, and corresponding bond pads are soldered with meltable balls to one of a plurality of metal leads perpendicular to the dice. The active surfaces of the dice may be coated with an insulative layer after lead bonding, and/or the entire multi-die device may be encapsulated.
U.S. Pat. No. 5,637,912 discloses a multi-chip module in which chips are stacked in a vertical arrangement, and a metallization pattern deposited on a surface formed by the chip edges.
MCM devices are also made which combine a number of dice side-by-side on a substrate. The conventional single in-line multi-chip module (SIMM) and dual in-line multi-chip modules (DIMM) are common examples of this MCM configuration. Other examples are shown in U.S. Pat. No. 5,137,836 to Lam, U.S. Pat. Nos. 4,992,849 and 4,992,850 to Corbett et al., U.S. Pat. No. 5,255,156 to Chang, U.S. Pat. Nos. 5,239,747 and 5,461,544 to Ewers, U.S. Pat. No. 5,465,470 to Vongfuangfoo et al., and U.S. Pat. No. 5,480,840 to Barnes et al.
U.S. Pat. No. 5,592,019 to Ueda et al. shows multiple single-chip packages connected on end to a substrate by their leads.
The y-axis stacking of multiple packaged devices has been used in an effort toward miniaturization. In U.S. Pat. No. 5,155,067, a multi-chip package is shown wherein packaged devices are stacked in a housing and sealed with a covering lid. The outer leads of the devices are connected by e.g. solder to conductive pads on the housing, and the pads are attached to e.g. DIP style leads for attachment to a circuit board.
A stackable carrier for chips is shown in U.S. Pat. No. 4,996,587 to Hinrichsmeyer et al. A single chip or die is adhesively positioned in an underside recess in the carrier and conductive wires from the die are passed through a hole and bonded to conductors formed on the upper surface of the carrier. S-shaped connector clips are soldered to each of the I/O leads on opposed edges of the carrier and to the clips of other carriers stacked with it to form a multi-chip package (MCM).
In U.S. Pat. No. 5,514,907 to Moshayedi, a multi-chip memory module has a plurality of stacked IC devices between opposing “side boards”, the latter comprising circuit boards with a pattern of interconnected vias into which the pins of the devices are soldered. The pins of the lowermost device are also soldered to the substrate, such as a main circuit board and comprise the interconnection between the module and the circuit board.
U.S. Pat. No. 5,420,751 to Burns discloses a stacked IC package which has vertical metal rails which pass through a cap above the packaged devices. Each rail is soldered to corresponding outer leads of the primary packages and has a lower end connectable to a PCB. The primary devices are adhesively joined to prevent movement of the devices in the stack package. Manufacture of the rails is a complex process, and the manipulation of a large number of parts to form the multi-IC package may be counterproductive.
In a later issued patent to Burns, U.S. Pat. No. 5,484,959, a stack package for thin small outline package (TSOP) devices is shown with vertical metal rails for each set of corresponding outer leads of the TSOP devices. A secondary “lead frame” for each TSOP package has secondary leads which are soldered to the pins of the TSOP package and to the metal rails. Each secondary lead is particularly formed with a “flex offset” to provide a stress relief connection with the rail.
As disclosed, the Burns apparatus requires a second lead frame for each packaged primary device. Furthermore, additional steps are required to form the stress relief offset. Furthermore, maintaining the rails in parallel non-contact alignment during and following soldering appears to be a major problem. A large number of soldering steps is required to join the large number of parts.
The aforementioned prior art patents disclose multi-chip apparatuses which are deficient in one or more of the following (or other) aspects:
a. The multi-chip module is complex to make, using a large number of parts which must be formed, aligned and individually secured in the device.
b. The y-dimension (perpendicular to the host PCB) of the multi-chip module is relatively great, and may be excessive for the particular end use.
c. Removal and replacement of a flawed primary device in the module is extremely difficult and may exceed the value of the module.
d. The inability to pre-test each primary device prior to incorporation into the multi-chip module results in an increased failure rate in the final multi-chip device.
e. The leads and connections result in excessive impedance effects at high clock speeds, i.e. greater than about 400 MHZ, and particularly at speeds now anticipated, i.e. about 800 MHZ and higher.
Among the many considerations in constructing semiconductor devices is thermal expansion. With multi-chip devices in particular, elasticity is required in the electrical connections to accommodate thermal expansion, as well as dimensional variation in the primary devices.
U.S. Pat. No. 5,600,183 to Gates, Jr. discloses a conductive adhesive comprising a mixture of e.g. silver powder in an epoxy material.
U.S. Pat. No. 5,468,655 to Greer discloses a temporary electrical connection comprising a metal paste applied to contact pads, then heated to partially melt the metal. A solder bump may then be placed in contact with the metal paste and heated to join the bump thereto.
BRIEF SUMMARY OF THE INVENTION
The present invention comprises a stack package connector by which a stack of primary packaged semiconductor devices is joined to provide a secondary package which is joinable to a printed circuit board or other host apparatus. In the invention, equivalent outer leads of the primary packages are joined by flexible conductive buses having low impedance and induction effects. One end of each bus is directly connectable to contact pads or other contact means of a host printed circuit board (PCB) or other electronic apparatus.
In one aspect of the present invention, a plurality of encapsulated integrated circuit packages is adhesively joined to provide a
Brooks Jerry M.
King Jerrold L.
Moden Walter L.
Clark Sheila V.
Micro)n Technology, Inc.
LandOfFree
Low profile multi-IC chip package connector does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low profile multi-IC chip package connector, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low profile multi-IC chip package connector will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2984805