Low noise and high performance LSI device, layout and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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C438S199000

Reexamination Certificate

active

07964454

ABSTRACT:
In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive
oise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

REFERENCES:
patent: 6461928 (2002-10-01), Rodder
patent: 6573172 (2003-06-01), En et al.
patent: 6939814 (2005-09-01), Chan et al.
patent: 7101742 (2006-09-01), Ko et al.
patent: 7105394 (2006-09-01), Hachimine et al.
patent: 7115954 (2006-10-01), Shimizu et al.
patent: 7176522 (2007-02-01), Cheng et al.
patent: 7470618 (2008-12-01), Sayama et al.
patent: 7545001 (2009-06-01), Cheng et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2003/0181005 (2003-09-01), Hachimine et al.
patent: 2005/0035470 (2005-02-01), Ko et al.
patent: 2005/0112817 (2005-05-01), Cheng et al.
patent: 2005/0151163 (2005-07-01), Hiyama et al.
patent: 2005/0186722 (2005-08-01), Cheng et al.
patent: 2007/0290208 (2007-12-01), Hiyama et al.
patent: 1445838 (2003-10-01), None
patent: 1638126 (2005-07-01), None
patent: 2003-92409 (2003-03-01), None
patent: 2003-0082934 (2003-10-01), None
Second Office Action dated Feb. 13, 2009 isued in corresponding Chinese Patent Application No. 200510063936X.
Ota, K., et al., “Novel Locally Strained Channel Technique for High Performance 55nm CMOS,” Tech. Dig. IEDM, p. 27-30, 2002.

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