Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2011-04-26
2011-04-26
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185170
Reexamination Certificate
active
07933151
ABSTRACT:
Memory strings includes: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround the first electric charge storage layer. First selection transistors includes: a second semiconductor layer extending upward from a top surface of the columnar portion; a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the second electric charge storage layer. The non-volatile semiconductor storage device further includes a control circuit that causes, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.
REFERENCES:
patent: 5599724 (1997-02-01), Yoshida
patent: 5707885 (1998-01-01), Lim
patent: 6411548 (2002-06-01), Sakui et al.
patent: 7619927 (2009-11-01), Cho
patent: 7683404 (2010-03-01), Jang et al.
patent: 7847334 (2010-12-01), Katsumata et al.
patent: 2007/0252201 (2007-11-01), Kito et al.
patent: 2007-266143 (2007-10-01), None
patent: WO 2009/075370 (2009-06-01), None
U.S. Appl. No. 12/684,349, filed Jan. 8, 2010, Itagaki et al.
U.S. Appl. No. 12/679,991, filed Mar. 25, 2010, Fukuzumi et al.
H. Tanaka, et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, IEEE Symposium on VLSI Technology Digest of Technical Papers, 2007, pp. 14-15.
Yoshiaki Fukuzumi, et al., “Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory”, IEEE International Electron Devices Meeting, 2007, pp. 449-452.
Iwata Yoshihisa
Maeda Takashi
Kabushiki Kaisha Toshiba
Nguyen Tan T.
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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