Low mask count process to fabricate mask read only memory device

Details Low mask count process to fabricate mask read only memory device Low mask count process to fabricate mask read only memory device

1998-04-09

2000-10-17

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438278, 438305, 438527, 257390, 257392, H01L 218236

Patent

active

061331015

ABSTRACT:
The present invention includes performing a blanket ion implantation to form lightly doped drain regions (LDD) adjacent to gate structures. A second ion implantation is performed with tilted angle to form p channel punchthrough stopping regions. A third ion implantation is used to implant ions into a NMOS device region. Oxide spacers are then formed on gate structures. Next, a forth ion implantation is then carried out to dope ions into the substrate to form source and drain regions in the NMOS region and a NMOS cell region, respectively. Next, a fifth ion implantation is used to dope dopant into a PMOS device region, thereby forming source and drain regions in the PMOS device region. Subsequently, a high temperature thermal anneal is performed to form shallow junction of the devices.

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patent: 5432106 (1995-07-01), Hong
patent: 5470774 (1995-11-01), Kunitgou
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patent: 5538914 (1996-07-01), Chiu et al.
patent: 5744394 (1998-04-01), Iguchi et al.
patent: 5759901 (1998-06-01), Loh et al.
patent: 5825686 (1998-10-01), Schmitt-Landsiedel et al.
patent: 5885873 (1999-03-01), Wu

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