Method for manufacturing a read only memory array

Details Method for manufacturing a read only memory array Method for manufacturing a read only memory array

1999-05-03

2000-10-17

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 218246

Patent

active

061331007

ABSTRACT:
A compact ROM array is formed in a single active region (5) bounnded by field oxide regions, the array being formed of one or more ROM banks (6, 7). Each ROM bank has a plurality of pairs of N+ bit lines (1-1 to 4-2), a plurality of conductive word lines (15-1 to 16-2) formed on top of, and perpendicular to, the bit lines, and left-select (11) and right-select (12-1, 12-2) lines arranged parallel to the word lines to enable particular transistor cells in the array to be selected to be read. The transistor cells (40, 41) are formed by adjacent portions of adjacent bit lines together with the portion of the word line extending between them. Isolation regions (43) between the transistor cells are formed by implanting the substrate between them with Boron dopant of a low energy and concentration after the bit and word lines have been fabricated and the transistor cells are programmed by implanting a channel region (42) with Boron of a higher energy and concentration after the low energy implantation step.

REFERENCES:
patent: 5526306 (1996-06-01), Hikawa et al.
patent: 5590068 (1996-12-01), Bergemont

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