Low-K dual damascene integration process

Details Low-K dual damascene integration process Low-K dual damascene integration process

2000-09-06

2001-11-27

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

Reexamination Certificate

active

06323123

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method for manufacturing the multi level interconnects of semiconductor devices, and more particularly to an integration process of a low-K dual damascene.
2. Description of the Prior Art
When semiconductor devices of integrated circuit (IC) become highly integrated, the surface of the chips can be not supplied with enough area to make the interconnects. For matching up the requirement of interconnects increase with Complementary Metal-Oxide-Semiconductor (CMOS) devices shrinks, many designs of the integrated circuit have to use dual damascene method. Moreover, it is using the three-dimensional structure of multi-level interconnects at present in the deep sub-micron region, and inter-metal dielectric (IMD) as the dielectric material which be used to separate from each of the interconnects. A conducting wire which connects up between the upper and the down metal layers is called the via plug in semiconductor industry. In general, if an opening which forms in the dielectric layer exposure to devices of the substrate in the interconnects, it is called a via.
It has two methods for conventional via and interconnect processes, one method is that via and interconnect finish by oneself, wherein the method is that the dielectric is first formed on the metal layer, and then the photoresist layer (PR) is defined on the dielectric, and use the etching process to make the via, and deposit conduction material in the via by means of deposition to finish the via process, then deposit and define metal layer, final, deposit the dielectric layer whereon. Conventional forming metal interconnect process is that make the via and the interconnect by means of two lithography process. Thus, it is need cumbrous steps of deposit and pattern. And yet, it will result in the interconnect to be difficult patterned due to the multi layer connect layout is more daedal in the sub-quarter micron.
Hence, damascene interconnect structure is developed at present. According to particular of the process, it will compartmentalize three types, such as the single type, the dual type and the self-aligned type. The damascene is a method that etch the trench of the interconnect in the dielectric, and then fill the metal as interconnect. This method can introduce metal that is difficult etched into the semiconductor without etching in the interconnect process. Therefore, this invention is the best method of the interconnect process in the sub-quarter micron.
Conventional dual damascene include two patterns, one is the deep patterns, that is the via patterns; another is the shallow patterns or the line patterns, that is the trench patterns. Referring to
FIG. 1A
, first of all, a dielectric
12
is formed over on the substrate
10
, and a etching stop layer
14
is formed over on the dielectric
12
, then a dielectric
16
is formed over on the etching stop layer
14
. And then a photoresist layer
18
is formed on the dielectric
16
, then the photoresist layer
18
is patterned as a deep pattern area. As show in
FIG. 1B
, dry etching of the deep patterns is proceeded by means of the photoresist layer
18
as a mask, then punch through the dielectric
16
, etching stop layer
14
and the dielectric
12
, and forming a via hole, then remove the photoresist layer
18
. As show in
FIG. 1C
, a photoresist layer
22
is formed on the dielectric
16
by deposition, and it is defined to form a shallow pattern area, and the partial surface of the via
20
and the dielectric
16
are exposed, likewise, the horizontal size of the shallow patterns is large more then one of the deep patterns. As show in
FIG. 1D
, dry etching of the shallow patterns is proceed by means of the photoresist layer
22
as a mask, and exposed partial surface of the dielectric
16
is removed to form a trench
24
having large horizontal size to take advantage of etching stop layer
14
is as a etching terminal point. As show in
FIG. 1E
, the photoresist layer
22
is removed to form the opening of the damascene
20
,
24
. Final, proceed a interconnect process, since the above processes are well known in the prior art, which are not the focus of the present invention, hence will not be described in greater details.
The skill of the dual damascene is a method for forming the via and the interconnects. For dual damascene application, the via fist integration scheme is not as sensitive to the lithographic alignment as the self-aligned scheme. However, when the second photoresist layer is formed, the residue of the photoresist layer will be found in the via. When the second photoresist layer or the residue of the photoresist layer is removed, it will hurt the surface of the low-K material.
In accordance with the above description, a new and improved method for fabricating the low-K dual damascene integration skill is therefore necessary, so as to raise the yield and quality of the follow-up process.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for fabricating the low-K dual damascene integration skill that substantially overcomes drawbacks of above mentioned problems arised from the conventional methods.
Accordingly, it is an object of the present invention to provide a new method for fabricating the low-K dual damascene process, the present invention use siloxane or methyl siloxane to be as the gap-filling material.
The other object of the present invention is to provide a new method for fabricating the low-K dual damascene process, so as to form the gap-filling material to avoid photoresist layer residue that produced in the via hole. Moreover, the gap-filling material is formed to avoid destroying low-K dielectric while removing the photoresist layer and photoresist residue. Thus, the method of the present invention is effective in raising quality of the process.
Another object of the present invention is that avoid long over etching the bottom of the via and destroying the desire conduct electricity area, so as to fill the gap-filling material in the via hole, and the gap-filling material is easy to remove by dry etching or wet etching after trench etching. Thus, the method of the present invention is easily and to conform to the economic effect, and it is suitable for use in the sub-micron.
A further object of the present invention is that can prevent the low-K materials contact with photoresist layer by fill the via with conventional partial-cured (or un-cured) siloxane (or methyl siloxane) and solve the photoresist rework problem described above.
In accordance with the present invention, a new method for fabricating low-K dual damascene is disclosed. In one embodiment of the present invention, a substrate having copper conduct electricity layers and dielectric layers is provided. First, a copper diffusion barrier layer is formed over the substrate by deposition, and a first inter-metal dielectric is formed over the diffusion barrier layer by deposition. A etching stop layer and a second dielectric are formed in turn over the first dielectric by deposition. Next, a hard mask is formed on the second dielectric. Then, a photoresist layer is formed over the hard mask, and defining the photoresist layer to be a deep pattern area. And then dry etching of the deep pattern is carried out by means of the first photoresist layer as the mask, and punch through in turn the hard mask, the second dielectric layer, the etch stop layer and first dielectric layer to form a via hole, then the photoresist layer and the hard mask are removed. A gap-filling material (such as siloxane or methyl siloxane) is filled on the second dielectric and into the via hole by conventional partial-cured (or un-cured) spin-on glass method (P-SOG). Subsequently, carrying out the etching back to the gap-filling material, and expose the surface of the second dielectric and gap-filling material. A anti-reflection layer (ARL) is formed over the second dielectric by deposition with the anti-reflection coating (ARC) to prevent the glisten of the surfac

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