Low inductance leadless package

Details Low inductance leadless package Low inductance leadless package

2000-03-20

2002-09-17

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S678000, C257S687000, C257S701000, C438S123000

Reexamination Certificate

active

06452255

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to the bulk packaging of integrated circuits. More particularly, the invention relates to leadless packaging designs and processes that inherently have relatively lower inductance.
A leadless leadframe package (LLP) is a relatively new integrated circuit package design that contemplates the use of a metal (typically copper) leadframe type substrate structure in the formation of a chip scale package (CSP). As illustrated in
FIG. 1
, in typical leadless leadframe packages, a copper leadframe strip or panel
101
is patterned (typically by stamping or etching) to define a plurality of arrays
103
of chip substrate features. Each chip substrate feature includes a die attach pad
107
and a plurality of contacts
109
disposed about their associated die attach pad
107
. Very fine tie bars
111
are used to support the die attach pads
107
and contacts
109
.
During assembly, dice are attached to the respective die attach pads and conventional wire bonding is used to electrically couple bond pads on each die to their associated contacts
109
on the leadframe strip
101
. After the wire bonding, a plastic cap is molded over the top surface of the each array
103
of wire bonded dice. The dice are then singulated and tested using conventional sawing and testing techniques.
FIG. 2
illustrates a typical resulting leadless leadframe package. The die attach pad
107
supports a die
120
which is electrically connected to its associated contacts
109
by bonding wires
122
. A plastic cap
125
encapsulates the die
120
and bonding wires
122
and fills the gaps between the die attach pad
107
and the contacts
109
thereby serving to hold the contacts in place. It should be appreciated that during singulation, the tie bars
111
are cut and therefore the only materials holding the contacts
109
in place is the molding material. The resulting packaged chip can then be surface mounted on a printed circuit board or other substrate using conventional techniques.
Although leadless leadframe packaging has proven to be a cost effective packaging arrangement, there are continuing efforts to further improve the package structure and processing to improve the performance of the resultant devices. One persistent issue in packaging generally is the need and desire to provide packaging designs that facilitate relatively low inductance devices. Accordingly leadless packaging arrangements that have generally lower inductance would be desirable.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and according to the purpose of the present invention, a variety of leadless packaging arrangements and methods of packaging integrated circuits in leadless packages are disclosed. In one aspect, a leadless semiconductor package is described having an exposed die pad and a plurality of exposed contacts that are formed from a common substrate material. The die attach pad, however, is thinned relative to at least a portion of the contacts. A die is mounted on the die attach pad and wire bonded to the contacts. Since the die attach pad is lower than the contact surface being wire bonded to, the length of the bonding wires can be relatively reduced, thereby reducing inductance of the device. A plastic cap is molded over the die and the contacts thereby encapsulating the bonding wires while leaving the bottom surface of the contacts exposed.
In some embodiments, the die is arranged to overhangs beyond the die attach pad towards the contacts. In other embodiments, a portion of at least some of the contacts are thinned to a thickness substantially similar to the die attach pad to form contact shelves. The die is then mounted such that it bridges the die attach pad to the contact shelves. These arrangements can also be used to relatively shorten the bonding wires. In some of the embodiments, reverse wire bonding is used to further shorten the bonding wires.
The described devices are packaged in bulk on a conductive substrate panel having at least one matrix of device areas defined thereon. Each device area includes a plurality of contacts and a thinned die attach pad. Individual caps are molded over each matrix of device areas prior to singulation of the devices.


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Leadless Leadframe Package (LLP), National Semiconductor Application Note 1187, Sep. 2000.

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