Low dielectric constant insulation in VLSI applications

Details Low dielectric constant insulation in VLSI applications Low dielectric constant insulation in VLSI applications

1994-04-28

1997-06-24

Niebling, John

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

4272555, 438624, 438631, H01L 2146

Patent

active

056417110

ABSTRACT:
A semiconductor device and process for making the same with reduced capacitance between adjacent conductors on a connection layer. This technique works best at narrow conductor spacing (less than 1 micron), where the need for lower dielectric constant intralayer insulation materials accelerates. Directional deposition of a dielectric layer 14 at an acute angle relative to the plane of a semiconductor substrate 10 forms bridges between the tops of narrowly spaced conductors 12, resulting in the formation of one or more gas dielectric regions 18. The process is self-aligning, using the shadowing effect of the conductors themselves to mask deposition of dielectric material between them, and only bridges between conductors which are closely spaced. Subsequent deposition of an interlayer dielectric 20 completes a typical structure. The directional deposition method may, for instance, be electron beam evaporation of a material such as SiO.sub.2, Si.sub.3 N.sub.4, polyimide, or amorphous Teflon.

REFERENCES:
patent: 5290358 (1994-03-01), Rubloff et al.
patent: 5310700 (1994-05-01), Lien et al.
patent: 5512775 (1996-04-01), Cho

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