Low-bias-deposited high-density-plasma...

Details Low-bias-deposited high-density-plasma... Low-bias-deposited high-density-plasma...

2001-09-05

2003-12-23

Ghyka, Alexander (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S783000, C438S784000, C427S579000

Reexamination Certificate

active

06667248

ABSTRACT:

BACKGROUND OF THE INVENTION
In conventional integrated circuit fabrication, circuit elements are formed by etching a pattern of gaps in a layer of metal, which are then filled with a dielectric. As efforts continue to include ever greater levels of integration on semiconductor chips, there has developed a persistent need to make circuit components (such as transistors, capacitors, etc.), smaller, bringing the components closer together, thereby allowing a greater number of components per unit of chip area. Increasing the component density on semiconductor chips results in increased sensitivity of operating speed and power consumption on the dielectric constant k of the material used to insulate the electrically conductive structures. If the dielectric constant is too high, the capacitance between the chip's metal lines becomes too large, creating undesirable cross talk across layers.
Various forms of silicon oxide or silicon-oxide-based glass are commonly used as the insulating material in integrated-circuit fabrication. While silicon oxide has an acceptably low dielectric constant for many applications, a lower dielectric constant is preferable for some applications, such as those involving a high density of circuit components. The lower dielectric constant reduces RC time delays, contributing to an overall improvement in the circuit's operation speed. One method of forming an insulator with a lower dielectric constant than undoped silicate glass (“USG”) involves adding fluorine to silicon oxide during a chemical-vapor-deposition (“CVD”) process. The presence of the fluorine dopants in the resulting fluorinated silicate glass (“FSG”) is known to have the desired lowering effect on dielectric constant.
Another factor to be considered in developing methods for depositing layers with appropriate dielectric constant is that copper, which has lower resistance than conventional aluminum alloys, is poised to take over as the main on-chip conductor for all types of integrated circuits. It is more difficult to etch copper than aluminum and a specialized process, referred to as a “damascene process,” has therefore been developed for the fabrication of copper-based integrated circuits. Thus, in damascene processes, dielectric layers are first deposited as an integrated stack, which is then etched to form gaps to be subsequently filled with the conductive material. A barrier layer, which can be overlying or underlying, is commonly included to prevent diffusion of copper into adjacent dielectric layers. Some integrated stacks used in damascene processes also use a layer known as an “etch stop” or “hardmask” to provide for selective etching of the layer. Silicon nitride (Si
x
N
y
) is a material commonly used for such applications, for example when forming vias between layers containing metal lines.
Deposition of USG and FSG layers for both gap-fill and damascene applications has previously been undertaken in high-density plasma (“HDP”) CVD systems. In such systems, deposition is accomplished by forming a plasma in a chamber from a mixture of gases containing the necessary elemental constituents of the desired layer. In the case of gap-fill applications, the wafer may be processed in the plasma while a bias is applied to the wafer. The bias accelerates ions from the plasma to the wafer so that the wafer is bombarded material that might prematurely close the gap is sputtered away while material from the plasma simultaneously deposits to fill the gap. The FSG gap-fill process is a generally good process scheme in terms of reliability, stability and throughput. HDP-FSG layers deposited in gap-fill applications have typically had a fluorine concentration of about 5.5-7.0 atomic percent (at. %) and a dielectric constant k of about 3.7, compared to a value of k about 4.0 to 4.3 for conventional undoped silicon oxides.
In addition to a sufficiently low dielectric constant, it is important that the material used for gapfill or damascene applications also have sufficient mechanical properties. For some applications, the material should have a hardness of at least 2.0 GPa and a compressive stress in order to minimize cracking.
Accordingly, it remains desirable to have a material that retains the oxide-like properties of good hardness and compressive stress of FSG while simultaneously having a lower dielectric constant.
SUMMARY OF THE INVENTION
Embodiments of the invention provide a method for forming a fluorinated silicate glass layer with HDP-CVD having a lower dielectric constant without compromising the mechanical properties of hardness and compressive stress. A gaseous mixture comprising a silicon-containing gas, an oxygen-containing gas, and a fluorine-containing gas is provided to a process chamber. The ratio of the flow rate of the fluorine-containing gas to the flow rate of the silicon containing gas is greater than 0.65. In some embodiments, the fluorine-containing gas comprises SiF
4
. A high-density plasma is generated from the gaseous mixture by applying a source RF power having a power density less than 12 W/cm
2
. A bias is applied to a substrate in the process chamber at a bias power density greater than 0.8 W/cm
2
and less than 2.4 W/cm
2
. The fluorinated silicate glass layer is deposited onto the substrate using the high-density plasma.
In some embodiments, the stability of the film may be increased by further including a nitrogen-containing gas in the gaseous mixture to deposit a nitrofluorinated silicate glass layer. In other embodiments, phosphorus-containing and boron-containing gases may also be included in the gaseous mixture.
In some embodiments, the fluorinated silicate glass layer is deposited on a silicon nitride barrier layer, which may have a hydrogen concentration less than 20 at. %. Such deposition of the silicon nitride layer and the fluorinated silicate glass layer may form part of a copper damascene process. In certain embodiments, a metal layer, such as TaN, is deposited on the fluorinated silicate glass layer after etching and ashing the silicate glass layer. In a particular embodiment, the ashing is performed with an O
2
chemistry. Before depositing the metal layer, the fluorinated silicate glass layer may also be cleaned with reactive H
2
.
Other deposition parameters may also be varied. In some embodiments, the high-density plasma is generated from the gaseous mixture my applying a source RF power having a power density less than 12 W/cm
2
and in other embodiments, the pressure in the process chamber is maintained above 11 mtorr.
The methods of the present invention may be embodied in a computer-readable storage medium having a computer-readable program embodied therein for directing operation of a substrate processing system. Such a system may include a process chamber, a plasma generation system, a substrate holder, a gas delivery system, and a system controller. The computer-readable program includes instructions for operating the substrate processing system to form a thin layer on a substrate disposed in the processing chamber in accordance with the embodiments described above.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.


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Shapiro, M.J., et al., “Dual Frequency Plasma CVD Fluorosilicate Glass Water Absorption and Stability,” DUMIC Conference; Feb. 1995, pp. 118-123.
Hayasaka N., et al., “High-Quality and Low Dielectric Constant SiO2 CVD Using High Density Plasma,” Dry Processing Symposium, vol. 2, Nov. 1993, pp. 163-168.
Fukada Takashi, et al.

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