Logic circuit testing with reduced overhead

Details Logic circuit testing with reduced overhead Logic circuit testing with reduced overhead

2011-08-09

2011-08-09

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000, C714S733000, C714S742000, C714S744000, C702S117000, C702S125000, C702S176000

Reexamination Certificate

active

07996743

ABSTRACT:
An integrated circuit may have a circuit under test. The integrated circuit may have a clock generation circuit that receives a reference clock from a tester and that generates a corresponding core clock. The integrated circuit may have a built in self test circuit and a clock synthesizer that receives the core clock. The built in self test circuit may provide clock synthesizer control signals that direct the clock synthesizer to produce test clock signals at various test clock frequencies. The test clock at the test clock frequencies may be applied to the circuit under test during circuit testing. The circuit under test may assert a pass signal when the circuit tests are completed successfully. The built in self test circuit may inform the tester of the maximum clock frequency at which the circuit under test successfully passes testing.

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