Logic circuit including a plurality of master-slave...

Details Logic circuit including a plurality of master-slave... Logic circuit including a plurality of master-slave...

2008-06-10

2010-12-07

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

With test facilitating feature

C326S009000, C326S093000

Reexamination Certificate

active

07847582

ABSTRACT:
According to an aspect of an embodiment, a logic circuit includes a first master latch included in one of the master-slave flip-flop circuits, the first master latch having a first scan data input for receiving scan data, the first master latch latching the scan data and outputting latched scan data, a second master latch included in another of the master-slave flip-flop circuits, the second master latch having a second scan data input operatively connected to receive an output of the first master latch, the second master latch latching the scan data inputted into the second scan data input and outputting latched scan data and a slave latch included in one of the master-slave flip-flop circuits, the slave latch having a scan data input operatively connected to receive an output of the second master latch.

REFERENCES:
patent: 6490702 (2002-12-01), Song et al.
patent: 7051255 (2006-05-01), Gschwind
patent: 7-198787 (1995-08-01), None
patent: 2000-214223 (2000-08-01), None

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