Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-09-28
2004-05-11
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000, C438S634000, C438S692000, C438S717000, C438S723000, C438S724000
Reexamination Certificate
active
06734097
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the use of a liner purposely having poor step coverage to improve the properties in W vias. The liner is characterized by appropriate adhesion for the W layer without increasing or widening the resistance values and spread respectively.
2. Description of The Prior Art
In general, semiconductors and integrated circuit devices will comprise a silicon substrate and a doped region(s) disposed in the semiconductor in which there are source or drain connections, separated by a gate or gate control region. Metal connections are made to the source, gate, and drain electrodes by interconnects that are supported over the substrate by an interlayer dielectric material.
Electrical connections are made between different layers by patterning and etching the dielectric to form contact and via openings. The openings are generally filled with electrically conductive materials of plugs made of W (tungsten) that contact previously doped regions, poly silicon or other metal layers. For example, a layer of physical vapor deposited (PVD) metal such as TiN is deposited in the sidewall of the contact/via openings to support adhesion of the electrically conductive material or plug of tungsten.
Since the ground rules or device geometry is getting increasingly smaller and the contact/via aspect ratios are becoming higher, step coverage of the TiN is becoming of increased concern because decreased step coverage requires the TiN layer to be thick enough to ensure sufficient deposition within a contact.
Further, in both single and dual damascene tungsten (W) interconnects contacting unlying metal layers, the contact resistance poses a problem because the W does not stick to oxide, thereby requiring the use of a liner to provide appropriate adhesion on the surface of the wafer; however, the problem is that the liner, which is generally made of TiN or a nitrogen treated Ti increases the contact resistance and also widens the resistance spread.
U.S. Pat. No. 5,625,231 discloses a process for improving the structural and electrical integrity of contacts and interconnects comprising metals deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) during processing of small ground rule semiconductor devices. The process entails: applying a TiN contact/via adhesion layer to a high aspect ratio contact/via opening etched in the dielectric by providing a first layer of TiN on the bottom of the contact/via opening and then depositing the second layer of TiN on the first layer of TiN and on the sidewalls of the contact/via opening. The second layer of TiN serves as the contact/via adhesion or glue layer.
A step coverage enhancement process for sub half micron contact/via is disclosed in U.S. Pat. No. 5,654,233. The improved step coverage method for the sub-micron or sub-half-micron contact/via is obtained by using the conventional PVD TiN deposition process coupled with a selective reactive etching process which etches off only the overhang.
U.S. Pat. No. 5,972,179 discloses a composite TiN barrier layer structure formed by depositing a first Ti layer by CVD to obtain good step coverage, followed by a second TiN layer formed by PVD to obtain uniform surface morphology for subsequent deposition of an aluminum alloy contact layer. By using a combination of these deposition techniques, with the last deposit made by PVD, the attributes of both deposition techniques are obtained, i.e. excellent step and bottom coverage characteristics of the CVD technique, and uniform morphology characteristics of the PVD deposition technique.
U.S. Pat. No. 5,654,589 discloses a process for forming multi layer interconnects that entails formation of Ti/TiN stack interconnect structures which may be used as local interconnects and contact landing pads on the same level. The local interconnects and contact landing pads directly contact conductive regions of a semiconductor IC. The contact may be formed with previously doped regions in the semiconductor substrate, polysilicon, or other metal layers.
U.S. Pat. No. 6,093,645 discloses a process for elimination of TiN film deposition in tungsten (W) plug technology using PECVD-Ti and in-situ plasma nitridation.
These patents improve the liner coverage to make sure the liner is covering all portions of the via. By doing this they fix the adhesion that is brought about by the W/oxide interfaces.
In the art of semiconductors where single and dual damascene W interconnects contacting underlying metal layers, where contact resistance is a problem, because the W does not stick to oxide, and wherein a liner is utilized to provide appropriate adhesion on the surface sidewall of the wafer, and wherein the liner (generally made of TiN or a nitrogen treated Ti) increases the contact resistance and also widens the resistance spread, there is a need for a liner that has very poor step coverage, that will coat the surface (to provide the necessary bulk adhesion for W) but have little or no coverage at the via bottom and via sidewalls so that there is improvements in via resistance and its spread.
The invention findings indicate that the vias themselves do not need to be coated with liner to achieve bulk adhesion.
SUMMARY OF THE INVENTION
One object of the present invention is to provide, in the case of a single damascene, where W interconnects contacting underlying metal layers and where the contact resistance is a problem, a liner with poor step coverage to improve the contact resistance in the W contacts.
Another object of the present invention is to provide, in the case of a dual damascene, where W interconnects contacting underlying metal layers and wherein the contact resistance is a problem, a liner with poor step coverage to improve the contact resistance in the W contacts.
A further object of the present invention is to provide, in the case of both single and dual damascene W interconnects contacting underlying metal layers and where the contact resistance is a problem because W does not stick to oxide and thereby requires a liner to secure adequate adhesion on the surface and sidewall of the wafer, a replacement of the traditional liner with a liner of poor step coverage which will coat the surface but have no coverage at the via bottom.
A further object yet still of the present invention is to provide, in the case of both single and dual damascene W interconnects contacting underlying metal layers and where the contact resistance is a problem because W does not stick to oxide and thereby requires a liner to secure adhesion to the surface and sidewall of the wafer, a replacement of the traditional liner with a liner that decreases the contact resistance and lessens the resistance spread, through the use of a very poor step coverage PVD TiN coating, so that coating of the surface is provided without coverage at the via bottom.
These and other objects of the present invention will be more particularly described in the brief description of the drawings and detailed description of the preferred embodiments of the invention.
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Iggulden Roy C.
Robl Werner
Shafer Padraic
Wong Kwong Hon
Deo Duy-Vu
Infineon - Technologies AG
Slater & Matsil L.L.P.
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