Linear feedback shift register, multiple input signature registe

Details Linear feedback shift register, multiple input signature registe Linear feedback shift register, multiple input signature registe

1997-10-15

1999-08-17

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

059387840

ABSTRACT:
A built-in self test (BIST) circuit using a linear feedback shift register (LFSR) and a multiple input signature register (MISR) requiring reduced circuitry exclusive of the number of inputs and outputs of the circuit to be tested. The BIST circuit is built in a prescribed circuit having a memory to test a target circuit in the prescribed circuit. The BIST circuit includes an LFSR, including a first logic section which is composed of a plurality of XOR gates and selection sections, and a first memory which is a part of the memory, for performing a primitive polynomial, an MISR, including a second logic section which is composed of a plurality of XOR gates and selection sections, and a second memory which is a part of the memory, for performing the primitive polynomial, and a BIST control section for controlling data input/output between the first and second memories and the target circuit and providing selection signals for controlling the selection sections in the first and second logic sections, the BIST control section controlling the target circuit and comparing operation results of the target circuit to perform the test of the target circuit.

REFERENCES:
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patent: 5588006 (1996-12-01), Nozuyama
patent: 5631913 (1997-05-01), Maeda
patent: 5703818 (1997-12-01), Osawa
patent: 5719913 (1998-02-01), Maeno

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