Line monitoring of negative bias temperature instabilities...

Details Line monitoring of negative bias temperature instabilities... Line monitoring of negative bias temperature instabilities...

2000-09-25

2003-02-18

Sherry, Michael (Department: 2829)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C438S018000

Reexamination Certificate

active

06521469

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to wafer-level reliability testing of semiconductor devices and, more particularly, to accelerated metal-oxide-semiconductor field effect transistor (MOSFET) testing for negative bias temperature instability (NBTI) effects.
BACKGROUND OF THE INVENTION
There are two major types of FET devices, the metal-oxide-semiconductor field effect transistor or MOSFET (also called an insulated-gate FET, or IGFET), and the junction-gate FET, or JFET. An FET has a control gate and source and drain regions formed in a substrate. The control gate is formed above a dielectric insulator that is deposited over the area between the source and drain regions. As voltage is applied to the control gate, free carriers in the substrate form a conduction channel in the region between the source and drain regions. Once the channel forms, the transistor turns “on” and current may flow between the source and drain regions.
Transistors are used as either amplifying or switching devices in electronic circuits. In the first application, the transistor functions to amplify small ac signals. In the second application, a small current is used to switch the transistor between an “on” state and an “off” state.
In recent years, the computer industry has experienced extremely rapid growth in all aspects, including number of units produced, breadth of applications, power and speed of operation, and complexity of computing machines. This growth is attributable to many factors, including remarkable increases in the number of active devices (typically transistors) included in the integrated circuit devices used in computers. By increasing the number of transistors in an integrated circuit device, the size of a computer may be reduced, or a more complex computer may be made within a particular computer case size. In addition, by increasing the number of transistors in an integrated circuit device, operational problems such as cross talk between physically adjacent conductors and signal propagation delays between different sections of the computer can be reduced. Further, integrated circuit devices are typically less expensive and more reliable than counterparts manufactured from discrete components. For these and many other reasons, the use of integrated circuit devices of increasing complexity has become the standard of the computer industry.
The trend toward more complex integrated circuits has resulted in increasing density of individual devices within the integrated circuit. To increase the number of individual devices within an integrated circuit, it is necessary to decrease the size of each individual device. The size of individual devices cannot be reduced arbitrarily. There are limitations to size reduction, including dimensional tolerance capabilities associated with manufacturing processes and various electrical phenomena that are associated with physical dimensions of the device. In addition, the essential need for high reliability of integrated circuits places limitations on shrinking the size of such devices. The steps of identifying these and other limitations and discovering techniques for ameliorating these limitations have made possible the increasing complexity of integrated circuits.
The prior art in the field of manufacture, testing, and use of MOSFET devices has identified several problems that occur during long-term use of such devices. Of particular concern is negative bias temperature instability (NBTI). NBTI in a MOSFET is a serious detriment to the long-term stability of the MOSFET, particularly p-type transistors and complementary metal oxide semiconductor (CMOS) devices having p
+
polycrystalline silicon gates. NBTI results from charge buildup at the silicon—silicon oxide interface and is due to the influence of negative voltages on the gate electrode of MOS structures. As explained in an article titled “Impact of Negative Bias Temperature Instability on the Lifetime of Single-Gate CMOS Structures with Ultrathin (4-6 nm) Gate Oxides,” by Shigeo Ogawa et al., appearing in the Japanese Journal of Applied Physics, vol. 35, pt. 1, no. 2B, page 1484 (1996), the phenomenon arises after long-term stressing of the MOSFET at elevated temperatures and generally occurs even in low fields (6×10
6
volts/cm or less).
This instability is particularly pronounced in p
+
polycrystalline silicon gate MOS structures, and was studied in the past extensively during the early stages of MOS transistor development. More recently, particularly with the development of high-speed MOS devices having gates with thin oxide layers, often less than 5 nm, there has developed a need for reliable testing techniques for such ultrathin oxides. One of the tests used to determine the life of devices having such thin oxide layers is a bias-temperature test and is based on NBTI of MOS structures. This test is performed at elevated temperature, although under constant voltage. The current state of the art achieves the necessary elevated temperature primarily by heating a wafer in a heating chuck. Such heating requires a long testing period to uniformly heat the wafer.
In U.S. Pat. No. 5,625,288 issued to Snyder et al., there is disclosed a different way to heat a test element. As shown in this reference, a polysilicon heater pad is placed near the test line. This configuration permits heating the test line without needing to raise the temperature of the full wafer. Although the placement of heating pads adjacent the test element provides an obvious reduction in the time needed to raise the temperature of the test element, particularly when the test element is a thin line that is placed along the length of the heating pad, this technique still involves conductive heating of the wafer area containing the test element. When the test element is a MOSFET, the pads must heat an area sufficiently large to contain the full transistor structure so as to assure that the gate oxide layer has reached the desired temperature. Consequently, the process is again time consuming.
There is thus a need in the art of reliability testing of MOSFET devices for improvement in the processes used to test for NBTI, which degrades the gate oxide of the MOSFET device, preferably without having to heat the full wafer on which the transistor is built. There is also a need for an NBTI test procedure that is sufficiently quick and cost-effective that the procedure can be applied to monitor NBTI on every lot in a semiconductor manufacturing line.
SUMMARY OF THE INVENTION
To meet these and other needs, and in view of its purposes, the present invention provides a process for in-line testing of a MOSFET device for NBTI. The process generally comprises four steps. First, a hole injection method is selected that produces approximately the same gate oxide degradation as the NBTI under test. Second, a correlation is established between the NBTI degradation and device shifts due to the selected hole injection degradation method. Third, an in-line procedure is developed based on the hole injection method, using the second step to relate the measured shift to NBTI. Finally, a NBTI specification is defined based on the hole injection method using the second step. The MOSFET device is preferably a p-type MOSFET device and the hole injection method is preferably a channel hot-carrier stress method.
It is understood that the foregoing summary and the following detailed description of the invention are exemplary, but are not restrictive, of the invention.


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C. Liu et al., “Mech

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