Limiting hydrogen ion diffusion using multiple layers of...

Details Limiting hydrogen ion diffusion using multiple layers of... Limiting hydrogen ion diffusion using multiple layers of...

2001-12-21

2003-07-22

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06596576

ABSTRACT:

BACKGROUND
The present invention relates to a method of forming gate structures comprising SiO
2
and Si
3
N
4
in the fabrication of semiconductors.
Electrical products with increased functionality require more storage and memory for performing the additional functions. Typically, conventional memories are composed of a MOS (Metal-Oxide-Semiconductor) transistor and capacitor, in which the MOS transistor generally comprises a source, drain, and gate. The gate is usually called a gate structure because the gate comprises layers of different materials, such as dielectric, metal and spacer layers. The spacer layers of the gate structure are applied as masks when forming a lightly doped drain (LDD) layer under the gate structure and positioned between the source and drain. The LDD layer is used to prevent the operations of the MOS transistor from interfering by the short channel or hot electron effects. In addition, the spacer layers are usually made of silicon nitride. Anisotropic etching is used to form the spacer layer that may result in increased leakage current.
FIG. 1
represents a typical gate structure comprising a gate oxide layer
101
, a polysilicon layer
102
, and a spacer layer
103
, which may be a silicon nitride cap layer, that are sequentially formed on a wafer to form the gate structure. In one version, the spacer layer is composed of a silicon oxide layer and a silicon nitride layer, such that the silicon oxide layer reduces stresses on the silicon nitride layer to prevent stripping of the layer. For example,
FIG. 2
shows a spacer layer, in which the thickness of silicon oxide layer
201
is in the range of 200 to 300 angstroms and the thickness of silicon nitride layer
202
is in the range of 400 to 800 angstroms, and this kind of the structure comprising SiO
2
and Si
3
N
4
layers is used in certain types of integrated circuits. For example, the E
2
PROM and Flash often use an ONO structure to serve as a dielectric layer between the floating gate and the control gate, where the “O” means the SiO
2
layer and the “N” means the Si
3
N
4
layer. This application utilizes the high dielectric constant of the Si
3
N
4
layer.
Typically, the SiO
2
/Si
3
N
4
layers are manufactured by low pressure chemical vapor deposition processes (LPCVD). In such LPCVD methods, a nitrogen-contained gas is reacted with a silicon-containing gas to deposit silicon-nitride on the substrate. Typically, the silicon-containing gas comes from the gas source, such as SiH
2
Cl
2
, Si
2
H
6
or SiH
4
; and the nitrogen-contained gas comes from ammonia (NH
3
). When SiH
2
Cl
2
and NH
3
gas are used as reaction gases in a LPCVD process, the chemical reaction is as follows:
3SiH
2
Cl
2(g)
+7NH
3(g)
. . . Si
3
N
4(s)
+3NH
4
Cl
(s)
+3HCl
(g)
+6H
2(g)
3SiH
4(g)
+4NH
3(g)
. . . Si
3
N
4(s)
+12H
2(g)
In semiconductor device manufacturing, the conductivity of a semiconductor material may be controlled by doping the semiconductor material with a dopant. The dopant source concentration and distribution affect the performance of the semiconductor devices. At high temperatures, thermal diffusion can cause the dopant region to expand or shift, thereby reducing the concentration of dopant in a dopant region. Extensive thermal diffusion can also cause the dopant region to close or overlap each other causing short channel and punch-through effects. The hydrogen produced when forming a silicon nitride layer by LPCVD may easily be adsorbed by the silicon nitride layer to act like a dopant material. At high temperatures, the hydrogen diffuses into the gate oxide and channel causing a threshold voltage shift of the MOS transistor.
Thus, it is desirable to have a structure of SiO
2
/Si
3
N
4
layers that reduces hydrogen atom diffusion into the gate oxide and channel to reduce any resultant degradation of the MOS transistor. However, with conventional methods of forming the SiO
2
/Si
3
N
4
layers it is difficult to control the adverse electrical effects that arise from impurity diffusion. Also, conventional methods have difficulty in solving pin-holing problems. It is desirable to have a method of manufacturing the SiO
2
/Si
3
N
4
layers to reduce adverse electrical effects arising from impurity diffusion especially for manufacturing highly integrated sub-micron semiconductor processes and to also reduce pin-holing effects.
SUMMARY
A method for fabricating a semiconductor device having a gate structure comprising SiO
2
and Si
3
N
4
comprises defining an active region on a substrate, forming an oxide layer on the substrate, forming a polysilicon layer on said oxide layer, forming a silicide layer on said polysilicon layer, defining the gate structure by etching the oxide layer, the polysilicon layer and the suicide layer, and implanting ions into the substrate using the gate structure as a mask. The method further comprises depositing a first deposition layer on the substrate, positioning the substrate in a reaction chamber, providing in the reaction chamber, an energized gas comprising a nitrogen component that reacts with a portion of the first deposition layer to form a silicon oxynitride layer on the first deposition layer, depositing a second deposition layer on the silicon oxynitride layer, and etching the first and second deposition layers and the silicon oxynitride layer to form multiple spacer layers against the gate structure.
A method for fabricating a semiconductor device having a gate structure comprising SiO
2
and Si
3
N
4
comprises defining an active region on a substrate, forming an oxide layer on the substrate, forming a polysilicon layer on the oxide layer, forming a silicide layer on the polysilicon layer, defining said gate structure by etching the oxide layer, the polysilicon layer and the silicide layer, and implanting ions into the substrate by using the gate structure as a mask. The method further comprises forming a first deposition layer on the substrate, forming a second deposition layer on the first deposition layer, positioning the substrate having the first deposition layer and the second deposition layer in a reaction chamber, performing an annealing process, forming a third deposition layer on the second deposition layer, and etching the plurality of deposition layers to form multiple spacer layers against the gate structure.
A method for fabricating a semiconductor device having a gate structure comprising SiO
2
and Si
3
N
4
comprises defining an active region on a substrate, forming an oxide layer on the substrate, forming a polysilicon layer on the oxide layer, forming a suicide layer on the polysilicon layer, defining the gate structure by etching the oxide layer, the polysilicon layer and the suicide layer, and implanting ions into the substrate by using the gate structure as a mask. The method further comprises forming a first deposition layer on the wafer, forming a second deposition layer on the first deposition layer, forming a third deposition layer on the second deposition layer, and etching the first, second and third of deposition layers to form multiple spacer layers against the gate structure.


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patent: 6268257 (2001-07-01), Wieczorek et al.
patent: 6309948 (2001-10-01), Lin et al.

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