Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2002-02-27
2004-01-06
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C174S255000
Reexamination Certificate
active
06674154
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a lead frame for use in a land grid array (LGA) type resin-encapsulated semiconductor device.
In recent years, a resin-encapsulated semiconductor device of a type called “QFN” (quad flat non-leaded package) has been developed in the art, in which an encapsulation resin is provided substantially only on the upper side of a lead frame (i.e., the lead frame is molded on one side), in an attempt to realize a small and thin resin-encapsulated semiconductor device. A conventional QFN type resin-encapsulated semiconductor device in which a die pad is exposed on the reverse surface of the package will now be described.
FIG. 11
is a cross-sectional view illustrating a conventional QFN type resin-encapsulated semiconductor device.
FIG. 12
is a plan view illustrating a lead frame used in the conventional QFN type resin-encapsulated semiconductor device. As illustrated in
FIG. 12
, the lead frame used in the conventional resin-encapsulated semiconductor device includes an outer frame
107
, or a frame body, having an opening therein, a rectangular die pad
101
placed substantially in the center of the opening, suspension leads
108
each having one end connected to a corner of the die pad
101
and the other end connected to the outer frame
107
for supporting the die pad
101
, and a plurality of inner leads
103
each extending toward the corresponding side of the die pad
101
. The conventional QFN type resin-encapsulated semiconductor device (package) includes the die pad
101
, the suspension leads
108
and the inner leads
103
of the lead frame, a semiconductor chip
102
bonded on the die pad
101
of the lead frame, thin metal wires
104
electrically connecting electrodes of the semiconductor chip
102
with some of the inner leads
103
, and an encapsulation resin
105
encapsulating the semiconductor chip
102
, the inner leads
103
, the thin metal wires
104
, the suspension leads
108
and the die pad
101
together on the upper side of the lead frame. Note however that the reverse surface of the die pad
101
, and the reverse surface and the outer side surface of each inner lead
103
are not covered with the encapsulation resin
105
but are exposed on the reverse surface or the side surface of the package. The reverse surface portion and the outer side surface portion of each inner lead
103
function as an external terminal
106
.
Note that although
FIG. 12
only shows, as a unit, a region of the lead frame on which one semiconductor chip is mounted, the entire lead frame actually includes a plurality of such units as illustrated in
FIG. 12
that are arranged next to each other in a matrix pattern.
Next, a method for manufacturing the conventional QFN type resin-encapsulated semiconductor device will be described.
FIGS. 13A
to
13
D are cross-sectional views taken along line XIII—XIII of
FIG. 12
, illustrating the method for manufacturing the conventional resin-encapsulated semiconductor device.
First, in the step of
FIG. 13A
, a lead frame as illustrated in
FIG. 12
is prepared, including the die pad
101
on which the semiconductor chip is mounted, suspension leads (not shown) for supporting the die pad
101
, and the inner leads
103
each extending toward the corresponding side of the die pad
101
(see FIG.
11
).
Next, in the step of
FIG. 13B
, the reverse surface of the semiconductor chip
102
is bonded on the upper surface of the die pad
101
via an adhesive, and the semiconductor chip
102
is mounted on the die pad
101
of the lead frame.
Next, in the step of
FIG. 13C
, the semiconductor chip
102
and a bonding region of the upper surface of each inner lead
103
are electrically connected to each other via the thin metal wire
104
.
Then, in the step of
FIG. 13D
, the lead frame having a number of semiconductor chips mounted thereon is set in an encapsulation mold set, with a sheet material (not shown) being closely held on an upper mold or a lower mold of the encapsulation mold set, and a resin encapsulation process is performed, whereby the semiconductor chip
102
, the inner leads
103
, the thin metal wires
104
, the suspension leads
108
and the die pad
101
are encapsulated in the encapsulation resin
105
on the upper side of the lead frame. At this time, the reverse surfaces of the die pad
101
and each inner lead
103
are exposed, i.e., not covered with the encapsulation resin
105
. Then, the lead frame is cut along the side surface of the encapsulation resin
105
so as to be divided into individual packages. In each package (resin-encapsulated semiconductor device), the reverse surface portion and the outer side surface portion of each inner lead
103
function as an external terminal
106
.
Although the above-described conventional QFN type resin-encapsulated semiconductor device has an innovative structure as a small and thin semiconductor device, there is much to be improved in order to accommodate a further increase in the number of pins of a semiconductor chip to be mounted and a further reduction in size. In view of this, an LGA type resin-encapsulated semiconductor device has been recently proposed in the art, in which external terminals are provided in two rows on the reverse surface of a package, in order to further reduce the size of the device and to increase the number of external terminals.
FIGS. 14A
to
14
C are an top view, a bottom view and a cross-sectional view taken along line XIVc—XIVc, respectively, each illustrating an LGA type resin-encapsulated semiconductor device proposed in the prior art.
FIG. 15
is a plan view illustrating a lead frame used in the LGA type resin-encapsulated semiconductor device. As illustrated in
FIG. 15
, the lead frame used in the conventional resin-encapsulated semiconductor device includes an outer frame
107
, or a frame body, having an opening therein, a rectangular die pad
101
placed substantially in the center of the opening, suspension leads
108
each having one end connected to a corner of the die pad
101
and the other end connected to the outer frame
107
for supporting the die pad
101
, a plurality of first inner leads
103
a
each extending toward the corresponding side of the die pad
101
, and a plurality of second inner leads
103
b
each extending to a position closer to the die pad
101
than the first inner leads
103
a.
As illustrated in
FIGS. 14A
to
14
C, the LGA type resin-encapsulated semiconductor device (package) includes a semiconductor chip
102
bonded on the die pad
101
, the first and second inner leads
103
a
and
103
b
, thin metal wires
104
electrically connecting the semiconductor chip
102
with the first and second inner leads
103
a
and
103
b
, and an encapsulation resin
105
encapsulating the semiconductor chip
102
, the inner leads
103
a
and
103
b
, the thin metal wires
104
, the suspension leads (not shown) and the die pad
101
together on the upper side of the lead frame. Note however that the reverse surface of the die pad
101
, the outer side surface and the reverse surface of each first inner lead
103
a
, the outer side surface of each second inner lead
103
b
, and the reverse surface of the tip portion of each second inner lead
103
b
are not covered with the encapsulation resin
105
but are exposed on the side surface or the reverse surface of the package. The reverse surface and the outer side surface of each first inner lead
103
a
, which are exposed respectively on the reverse surface and the side surface of the package, function as a first external terminal
106
a
. The reverse surface of each second inner lead
103
b
, which is exposed on the reverse surface of the package at a position closer to the die pad
101
than the first external terminal
106
a
, functions as a second external terminal
106
b
. Note that a lower portion of each second inner lead
103
b
is removed through a half-etching process except for the tip portion thereof, so that the second inner lead
103
b
has a reduced thickness in the half-etched portion.
Note
Kawai Fumihiko
Minamio Masanori
Nomura Toru
Cruz Lourdes
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Talbott David L.
LandOfFree
Lead frame with multiple rows of external terminals does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Lead frame with multiple rows of external terminals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lead frame with multiple rows of external terminals will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3218387