Layout of ESD input-protection circuit

Details Layout of ESD input-protection circuit Layout of ESD input-protection circuit

1995-11-13

1998-09-22

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257361, 257360, 257363, H01L 2362

Patent

active

058118560

ABSTRACT:
An object of this invention is the creation of an input protection circuit for highly dense integrated circuits that has improved ESD immunity. This is accomplished by the addition of a P.sup.+ diffusion adjacent to the emitter of a field device to make the base resistance of each of the field devices approximately equal. When an ESD source is contacted to the input protection circuit, the field devices will conduct simultaneously and with equal currents, thus preventing high current densities that can cause circuit failure.

REFERENCES:
patent: 5140401 (1992-08-01), Ker et al.
patent: 5151767 (1992-09-01), Wong
patent: 5182220 (1993-01-01), Ker et al.
patent: 5623156 (1997-04-01), Watt
"A Low Voltage Triggering SCR for Chip ESD Protection at Output & Input Pads" by Chitterjee et al, IEEE 1990, Symposium on VLSI Tech. pp. 75-76.
"ESD Protection for Submicron CMOS Circuits, Issues and Solutions", by Rountree in 1988 IEDM Technical Digest, pp. 580-583.

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