Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2008-02-21
2010-11-02
Clark, Jasmine J (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S773000, C257S775000, C257S776000, C257SE21030, C257S021000, C430S311000
Reexamination Certificate
active
07825525
ABSTRACT:
An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.
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patent: 6875703 (2005-04-01), Furukawa et al.
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Furukawa Toshiharu
Hakey Mark Charles
Holmes Steven J.
Horak David V.
Koburger III Charles William
Clark Jasmine J
International Business Machines - Corporation
Percello, Esq. Louis J.
Tutunjian & Bitetto PC
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